Honore Djieutedjeu
Rio Rancho,USA
Summary
- Staff Technology Development Engineer | Semiconductor Process Integration | Advanced Memory & 3DIC Solutions | Spintronics background| Solid State Chemistry | Data Analysis(JMP, SQL) | Scientific and Technical Writing | Self Motivated, Self Starter
- Semiconductor Technology Development Expert with a Ph.D. in Materials Science and Engineering and extensive experience in process integration, yield engineering, and new product development. Led pathfinding teams and delivered industry-first less than 50nm bitcell embedded DRAM using Thin Film Transistor based on IGZO.
- Contribute to TSV/TDV scaling, and hybrid bonding for next generation of Intel products and multiple generations of phase change memory or 3DXP products.
Overview
12
12
years of professional experience
Work History
Staff Technology Development & Integration Yield Engineer
Intel Corporation
08.2024 - Current
- Lead Three Dimensional Integrated Circuit(3DIC) development focusing on via-middle and via-last integration challenges, Through Silicon Via(TSV)/Through dielectric Via(TDV) scaling, and hybrid bonding roadmap.
- Established cross-functional team to enable backside Through Silicon Via for power delivery
- Involved on Die to die Through Silicon Via development for Signal processing
- Lead and drive focus team for program mission and New Product Introduction and development
- Report weekly on transfer progress to upper management and company executive
- Present technical challenges to technical staff and plan solutions and executions
Staff Technology Development & Integration Yield Engineer
Intel Corporation
04.2022 - 08.2024
- Owned integration scaling strategies for embedded DRAM using IGZO and derivatives.
- Owned integration strategy for HBM using low leakage DRAM
- Developed high aspect ratio (HAR) TSV and hybrid bonding processes for next-gen Intel products.
- Delivered industry’s first low-leakage high-density memory with significant scaling improvements.
- Report weekly on transfer progress to upper management and company executive.
- Present technical challenges to technical staff and plan solutions and executions.
Technology Development Process Integrator
Intel Corporation
09.2017 - 04.2022
- Led one of the Intel segments in JDP with Micron to develop 2nd-gen Intel 3DXP memory.
- Improved CMOS and structure 3DXP yield from 70%.
- Managed technology transfer and process matching between Fabs while transferring the technology we developed in Micron fab to Intel fab .
- Report weekly on transfer progress to upper management and company executive
- Present technical challenges to technical staff and plan solutions and executions
Postdoctoral Fellow
University of Kentucky
01.2016 - 08.2017
- Developed new materials and heterostructures for low-power electronics.
Visiting Lecturer
Indiana University Southeast
01.2015 - 06.2017
- Taught fundamental and advanced chemistry courses.
Postdoctoral Research Associate
University of Michigan
01.2014 - 12.2014
- Focused on spintronics materials research and magnetic semiconductors.
- Mentored and introduced new graduate, undergraduate and high school student in lab techniques, fundamental of spintronics and chalcogenide materials synthesis.
- Drafted and published technical papers, contributed to National Science Foundation proposal writing.
- Involved on multiple peer review papers from multiple materials science and chemistry journals
Education
Ph.D. - Materials Science & Engineering
University of Michigan
Ann Arbor, MI12-2013
Ph.D. - Chemistry
University of New Orleans
New Orleans, LA08-2011
M.S. - Chemistry
University of Yaoundé I
Yaounde, Cameroon02-2005
B.S. - Chemistry
University of Dschang
Dschang, Cameroon02-2001
Skills
- Semiconductor Process Integration
- Yield/Device/Reliability Engineering
- Materials Science & Thin Films
- TSV/TDV & Hybrid Bonding
- DOE & Data Analysis
- Simulation Tools (SEMulator3D, Cadence, KLayout)
- Leadership & Cross-functional Collaboration
Affiliations
- Materials Research Society (MRS)
- IEEE
- American Chemical Society (ACS)
- AAAS
Timeline
Staff Technology Development & Integration Yield Engineer
Intel Corporation
08.2024 - Current
Staff Technology Development & Integration Yield Engineer
Intel Corporation
04.2022 - 08.2024
Technology Development Process Integrator
Intel Corporation
09.2017 - 04.2022
Postdoctoral Fellow
University of Kentucky
01.2016 - 08.2017
Visiting Lecturer
Indiana University Southeast
01.2015 - 06.2017
Postdoctoral Research Associate
University of Michigan
01.2014 - 12.2014
Ph.D. - Materials Science & Engineering
University of Michigan
Ph.D. - Chemistry
University of New Orleans
M.S. - Chemistry
University of Yaoundé I
B.S. - Chemistry
University of Dschang
SELECTED PUBLICATIONS
- 1) Lone-Electron-Pair Micelles Strengthen Bond Anharmonicity in MnPb1δSb1δS3δ Complex Sulfosalt Leading to Ultralow Thermal Conductivity, Lamia Dahwahe, Ruiming Lu, Honore Djeutedjeu, Juan Lopez, Trevor P. Bailey, Brandon Buchanan, Zhixiong Yin, Citrad Uher, and Pierre F.P. Poudeu; ACS Appl. Mater. Interfaces 2020, 12, 40, 44991–44997, https://doi.org/10.1021/acsami.0c12938
- 2) Charge Disproportionation Triggers Bipolar Doping in FeSb2-xSnxSe4 Ferromagnetic Semiconductors, Enabling a Temperature-Induced Lifshitz Transition; Honore Djeutedjeu, Juan S Lopez, Ruiming Lu, Brandon Buchanan, Xiaoyuan Zhou, Hang Chi, Kulugammana GS Ranmohotti, Citrad Uher, Pierre FP Poudeu, Journal of the American Chemical Society,2019,141, 23, 9249–926, https://doi.org/10.1021/jacs.9b01884.
- 3) Engineering Magnetic Transitions in Fe1−xSnxBi2Se4 n-Type Ferromagnetic Semiconductors through Chemical Manipulation of Spatial Separation between Magnetic Centers; Juan Lopez, Honore Djeutedjeu, Brandon Buchanan, Kulugammana G.S. Ranmohotti, Alexander Page, Citrad Uher, and Pierre F.P. Poudeu, Chem. Mater. 2019, 31, 9, 3507–3518, https://doi.org/10.1021/acs.chemmater.9b00784
- 4) Crystal structure and thermoelectric properties of the 7,7L lillianite homologue, Pb6Bi2Se9; Casamento, Joseph ; Lopez, Juan; Moroz, Nicholas; Olvera, Alan; Honore Djeutedjeu; Page, Alexander; Uher, Citrad; P. Poudeu, Pierre, Inorg. Chem. 2017, 56, 1, 261–268, https://doi.org/10.1021/acs.inorgchem.6b02118
- 5) Co-existence of high-Tc ferromagnetism and n-type electrical conductivity in FeBi2Se4; Kulugammana Ranmohotti
- Honore Djeutedjeu, Juan Lopez, Alexander Page, Neel Haldolaarachchige, Hang Chi, Pranati Sahoo, Citrad Uher, David Young, Pierre Ferdinand Poudeu Poudeu; Journal of American Chemical Society, 2015, 137(2), pp 691 – 698. (Highlighted as Press release in Michigan News and selected as the ten best spintronics story 2015 by spintronics info).
- 6) High-Tc ferromagnetism and distribution of Magnetic centers in Fe1-xSnxSb2Se4 semiconductors; Honore Djeutedjeu, Clarina De La Cruz, Alan Olvera, Alexander Page, Neel Haldolaarachchige, David P. Young, Pierre F. P. Poudeu, Inorg. Chem. 2015, 54, 21, 10371–10379. https://doi.org/10.1021/acs.inorgchem.5b01753
- 7) Donor and acceptors impurities switching of magnetic ordering in MnSb2-xSnxSe4; Honore Djeutedjeu, Xiaoyuan Zhou, Neel Haldolaarachchige, Kulugammana G. S. Ranmohotti, Citrad Uher, David Young, Pierre Ferdinand Poudeu Poudeu, Journal of Materials Chemistry C, 2014, 2, 6199 – 62210.
- See the link below for full publications. https://scholar.google.com/citations?user=e7qNCPQAAAAJ&hl=en.
Key Accomplishments details
- Intel Corporation:
- NSG Strategy Acceleration Division Recognition Award (Q1 2019) Recognized for improving product yield from 70%.
- IOG Technology Development Award (Q4 2020) Defined new product requirements from a process integration and materials selection perspective.
- IOG Department Recognition Award (Q3 2021) Enabled processes that resolved multiple products issues and improved yield from 0% to >30%.
- IOG Innovation Excellence Award (Q3 2021) Developed metrology solutions to detect sources of variation and resolve inline issues.
- IOG Experiment Excellence Award (Q3 2021) Delivered segmentation and defect reduction strategies, achieving ~60% yield improvement.
- IOG Group Recognition Award (Q2 2021) Contributed to new product yield enablement and cost reduction.
- IOG Innovation Excellence Award (Q4 2021) Developed nitrogen-doped carbon with lower stress and higher etch rate, eliminating carbon implant step and saving $35 per wafer, improving uniformity and closing MTS gap.
- Experimental Excellence Award (Q4 2021) Optimized etching and hybrid seal development to close MTS gaps and enable downstream optimization.
- Distinguished Invention Award (Q1 2022) Invented a method to encapsulate phase change materials (PCM) for improved reliability.
- Superior Department Award (Q1 2022) Ran comprehensive DOE tests to identify tuning knobs for etch rate, H2 deco, and precursor quality improvements.
- D1D Department Division Award (Q4 2024) Developed industry’s first scaled low-leakage embedded DRAM with ~4× lateral density increase compared to baseline product.
Honors & Awards
Multiple Intel awards for innovation, yield improvement, and cost reduction., NSF grant recipient ($600K) for chalcogenide research., Published 30+ papers and secured 11 patents/trade secrets.