JOANNE ATHAIDE

• Verification of Message engine subsystem within MTIA

MTIA is an inference accelerator that is meant to handle all of Meta's internal AI workloads. I worked on the messaging engine subsystem that carried out collectives in a performant manner. The architecture supports parallel execution of collective operations using multiple resources like NICs, CPU-M, sub-graph manager, and NMC. HCCL divides operations into SubGraphs for efficient resource utilization.

• Verification Network Interface Card ASIC

Full ownership of Transmit queue manager block. Built a constrained random UVM test bench from scratch in a reusable manner so as to be included in top-level verification. Interacted with cross-functional members from architecture, design and driver teams to bring the block to closure. Coordinated with other DV block owners on common components.

Mentored junior engineers in DV activities

Register layer automation scripts in python

• Verification of Video Encoder: H264 and VP9 codecs

Owned 3 blocks within the video encoder pipeline: Deblocking filter, Integer Motion Estimation, Command DMA. Drove them to closure. Worked on AXI and AHB interface BFM.

Built a random stimulus generator using SV constraints to generate random motion vectors which were used by multiple blocks in the pipeline for coverage closure.

• Built a DVS (data-valid-stall) coverage tool using Python and System Verilog UVM.

• Verified the RX PCS based on Clause 82 of IEEE 802.3 on 100G and 40G Ethernet IP
• Lead a team including offshore CW's on verification of Auto-negotiation (Clause 73) and Link Training logic (Clause 72, 93 of IEEE 802.3).

Test plan creation, test writing, results and coverage tracking. Enabled a team in Penang to reuse our tests + testbench for verifying the above features on 10G/25G, hence saving 6-8 weeks of effort.

• Lead the testbench architecture and test plan creation for "Dynamic reconfiguration" feature.

This feature changes the previous static speeds and mode to dynamically switch between speeds: 100G, 25G, 10G and modes: full stack (MAC+PCS), PCS only, OTN, FLEXE. We scaled our existing bench to work for multi-channel architecture hence reusing existing tests.

• Verification of Saas FPGA for Bing search acceleration (System verilog UVM)

The Data Access Layer within the Saas FPGA handles posting list access requests from higher layers and fetches corresponding index from a memory hierarchy that is composed of on-chip RAM, on board DDR and host memory. In previous versions, verification stimulus was a simple playback of query files. I helped with the generation of synthetic stimulus data in the form of a system verilog library for verifying the system. This helped in achieving 100% code and functional coverage by testing all possible corner cases.

• Verified the MAC and Statistics blocks (System Verilog-UVM)

Verified IEEE 802.3 clause 3 - Ethernet MAC layer involving frame packaging and processing along with several custom features. Register readable MAC statistics were functionally verified.

• Verified the MACSEC block compliant with IEEE 802.1AE (System Verilog-UVM)

Responsible for verification of the highly complex receive classifier that would preprocess the frames and extract useful information that would be used by the GCM-AES core.

• RTL Design of MDIO (Verilog)
• Bug analysis tool for mining data from Bugzilla (Perl) (Individual project)
• Verified Layer 1 Fibre Channel compliant with FC-FS-6 (System Verilog-UVM)

Verified from testplan to coverage closure: 32G and 16G fibre channel using 64b/66b transmission word format and 8G, 4G and 2G fibre channel 8b/10b transmission word format.

• Verification of Energy Efficient Ethernet in the Low Speed Physical Coding Sublayer(LS PCS) compliant with Clause 36 of IEEE 802.3 (System Verilog-UVM) (Individual project)
• Integrated third party Avago 16nm and 28nm Serdes IP and BPAN (Backplane auto-negotiation) with our universal MAC IP for interoperability testing.

• Implemented several Computational algorithms for image processing using MATLAB.

• Worked towards research project titled "Learning Environment through Communicating Mobile Robots" part of IEEE Intl. Conf. on Intelligent Computing and Intelligent Systems (ICIS 2009).
• Responsible for adding "vision" to previously sensor based robots.
• Successfully implemented several enhancements to the robotic system such as line follower, color detectors, face detection.