Kartik Patel

• Develop and validate critical PCIe features, ensuring compliance with PCIe specifications and industry standards.
• Conduct performance validation of PCIe IP Gen6 and earlier versions.
• Collaborate closely with architects to determine bandwidth modeling and optimize system performance to achieve at least 98% of theoretical targets.
• Manage features such as receiver overflow and address translation for PCIe Gen5.
• Optimize validation infrastructure, reducing runtime for performance-related tests by 50%.

• Responsibilities include creating robust testplan and developing directed, random and cross traffic tests for Intel's Network on chip fabric
• Supporting RAL (Register abstraction Layer) infrastructure at SOC
• Responsibilities also included testing the security attribute feature of the fabric
• This testing made sure that no external illegal entity can access register through the fabric and only Legal keys are able to access the Endpoint (IPs)
• This testing was also extended to emulation wherein the role was to create a verification framework that mimics the behavior of the tests written in OVM
• The developed framework exhaustively verified all corner cases and scenarios by doing sweep testing
• Post processing scripts were also developed as part of the framework to ascertain connectivity of all eps to the NOC fabric, thus eliminating human error.