Khaled Pakizeh

Simple ARQ Protocol

Implemented the stop-and-wait ARQ protocol which is a half-duplex mode under FDD (Frequency Division Duplexing). This project used a non-coherent demodulator for DSPK (Differential Phase Shift Keying) modulated packets. Each packet is constructed as follows: start (signature sequence for acquisition), middle (data payload), and end (CRC - Checksum). The application threads consist of: Modulation and Pulse shaping, Detector, Matched filter, Correlation, and Demodulation.

Project Used: Digital communication theory, C programming, pthread APIs, semaphores, linux system programming, and UHD (USRP Hardware Driver which is a C driver to program the radio - F.W for the radio).

Detection of Counterfeit IC - FPGA (in progress)

Created a I2C driver using Verilog on a target board (i.e., board susceptible to counterfeit IC) to read a temperature sensor. Intercepted the communication lines between the sensor and target board using a Microchip controller and altered the sensor data. Next steps will involve a Interrogator board to detect the counterfeit IC.

Project Used: Verilog, ModelSim, ICE40HX1K (lattice FPGA), PmodTmp3 (Digilent I2C temperature sensor), and Cyclone V SOC FPGA (Altera FPGA), and PIC microcontroller.