Kiran Kumar Ravoori

VCS Simulator:

• Key player in securing a crucial customer account renewal by addressing simulation issues, tool-related challenges, and implementing advanced VCS features. Acknowledged by both management and the customer.

PrimeTime STA and Prime* Products:

• Created an innovative system for identifying unique failures, enhancing product reliability.

• Introduced "triAll," a system reducing customer release migration time by 50%.

• Developed an automated tool to capture software release settings, benefiting field and PV/PE engineers.

• Hired technical professionals and trained them on a systems I developed for customer release qualifications, flow testing, and debugging for PrimeTime tool issues and other products.

• Designed a novel Python testing methodology for detecting flow-related bugs in PrimeTime STA.

• Direct Collaboration with Synopsys Fellow - RTM2.0 Development: Worked directly with a Synopsys Fellow to develop the RTM2.0, a Python-based SystemVerilog object model, serving as the primary testing framework for advanced technologies in the VCS simulator
• Collaborated with DevOps teams to establish a 24x7 regression model and improve the testing framework for VCS and Verdi, enabling comprehensive testing of various features and flows
• Conducted knowledge transfer sessions to build expertise across teams for RTM2.0, facilitating effective test creation
• Created various test mutations by loading tests into the object model, iterating them, and generating test mutations to enhance functional coverage without increasing the disk footprint
• Developed Xforms for SystemVerilog Constraints, Functional Coverage, XMRs, Random Stability, X Propagation, Low Power, FSDB, Verdi(KDB), and DPI
• XMR Test IP: Designed an XMR test IP using a Python object model for SystemVerilog, significantly enhancing VCS XMR tool quality and leading to the discovery of over 1000 bugs
• Additionally, provided guidance to the teams for further refinement of the testing framework.

• Innovative Testing Methodologies: Developed the Random Testing Methodology 1.0 (RTM1.0) in Perl to randomize parameterized Verilog/System Verilog and VHDL constructs
• Clock Tree Random Operator: Designed and implemented a random operator module, achieving major performance optimization and glitch detection
• Algorithm-Based Testing: Collaborated with VCS architects to develop algorithm-based tests for VCS technologies.

• Specialized in VCS Technologies: Focused on VCS Partition Compiler and Radify Technologies, with expertise in SDF, Dynamic Reconfig, Dynamic Testbench loading, and more
• Technical Collaboration: Worked closely with a Synopsys Fellow to develop tests for Zebu (Emulation) Swave power and Sequential technologies.

• Gained extensive experience working on various VCS technologies, including Partition Compile and Pre-compile IP.