Summary
Overview
Work History
Education
Skills
Websites
Personal Information
Timeline
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Kishan Sarpangala

Kishan Sarpangala

Austin,TX

Summary

I have total of 9+ years experience in SOC Design. Well versed in different aspects of chip design. Strong knowledge in Verification, DFT, Validation and Firmware. Comfortable with Linux environment.

Overview

16
16
years of professional experience

Work History

Principal System Engineer

NXP
04.2023 - Current
  • Part of the Architecture Verification team which does Bootrom, Security, Boot, Safety, PCIe, Debug, Trace and System verification of Automotive chips on emulator (ZEBU)
  • Support the design of end-to-end system architecture.
  • Did performance architecture analysis using complex cycle accurate performance model/FPGA.
  • Verify lifecycle checks on Fuses, Root of trust, Secure boot, cryptography & Trust zone - an important verification stage for product development team.
  • Also verify secure trust firmware for ATE/FAB.
  • Design and implement cryptography-based security features related to data encryption, Device Attestation, and other cryptographic protocols.
  • Enabled PCIe features like CDMA, Route by Port and Route by Address, link training and PCIe to CPU to LPDDR access.
  • Experience designing and/or implementing secure systems, including activities involving security architecture, protocol design, cohort security.
  • Debug and optimize firmware on SoC platforms, participate in the bring-up of FPGA/ASIC systems, ensuring that security features are functional.
  • Experience in languages relevant to cryptographic implementation.
  • Experienced in pre-silicon performance analysis, including Profile Experience simulation/emulation platforms.
  • Experienced in verifying Streaming Scan Network (SSN), MBIST and repair scheme implementation, JTAG/IJTAG, back-annotated gate level verification, silicon debug.
  • Develop test-cases to verify features in a co-simulated and emulated/FPGA hardware environment, end-to-end firmware and hardware feature validation.
  • Experience debugging software using debuggers and trace files.
  • Validating hardware features for at least 2+ projects in a pre-silicon environment.
  • Debugging failures using waveform viewers, log files and microcode trace dumps.
  • Knowledge of Image generation, Core boot.
  • Part of the team involved in Security Architecture Design and Security Verification and developing secure protocols.
  • Hands-on experience with ARM hardware debug, profiling, and trace.
  • Understand and analyze the impact of system-level architectural trade-offs.
  • Proficient in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation.
  • Developed smart stubing script in Perl, developed force/deposit based script to be used by build team.
  • Knowledge of the Arm Architecture.
  • Wrote CMM or debug scripts for debug activities of JTAG features.
  • Developed test cases in C, TCL, python for boot flow and verified various boot scenarios on emulator.
  • Verified fuse, firmware, and system features like reset and power.
  • Debugged environment and emulator model issues.
  • Enhanced the existing firmware image generation scripts.

Staff GPU Firmware/Embedded lead Engineer

AMD
06.2020 - 04.2023
  • I had two different roles at AMD - Staff Embedded Software Lead & also worked as Debug/Fuse lead in Validation team.
  • Extensive experience in debug and validation roles involving OS, FW, Silicon, and HW issues, with a strong emphasis on GPU technologies.
  • Experience with multiple debug methodologies from System/OS level down to RTL level.
  • Ran performance benchmarks by using AI and ML workload/algorithms using industry standard frameworks, and libraries.
  • As Firmware/Embedded Technical Lead: I was involved in defining Firmware boot sequence and security features for GPU HPC ML products like MI and NAVI series.
  • Hence, comfortable with boot flow, cryptography concepts and GPU architecture.
  • PCIe Link training, LTSSM debug and Bringup PCIe features on silicon.
  • Experience with ASIC power state definition and optimization techniques, such as power gating, clock gating, dynamic voltage and frequency scaling.
  • Collaborate with cross-functional teams to define and develop secure chip architectures.
  • Perform security reviews and implemented cryptographic algorithms & supervise the development of power management features.
  • PCIe Enumeration bring up and PCIe features bring up in ATE.
  • Well versed with PMFW, mini-PMFW and PPTable features.
  • Owned several GPU product's security feature bring-up and post silicon debug.
  • Used Pre-silicon shift left techniques and platforms to develop and validate system/firmware/driver functional features using platform simulator (S), which includes C/C++ model and have extensively used Emulator.
  • Ensured that GPU block functional modeling via test/regression to ensure functional validity for next generation.
  • Used GPU's Functional Design Verification/ Simulation environment - GPU microarchitecture-based HW-SW co-verification (GPU full-featured functional C model).
  • Maintaining the integrity of GPU Firmware basically stressing the functional model via adding automated tests to daily regression.
  • Developed cryptographic algorithm & implementation.
  • Experience Working closely with colleagues and internal customers to ensure needed features are implemented as specified in the functional architecture/design specification.
  • Wrote and maintained automation infrastructure (regressions) (Python).
  • I have used C and Python language to automate and implement various embedded features extensively.
  • Very comfortable in writing complicated python code/provide infrastructure support for system validation.
  • Wrote Python scripts which does system monitoring and passionate about automated testing.
  • Performance Analysis Lead in Validation Team: Proficiency in Python/C++ for modeling, analysis, and automation; familiarity with ML frameworks.
  • I worked with several stakeholders to define fuse and Power definition for MI200 chip.
  • I have validated firmware features on emulator and C++ model.
  • Created AVFS fuse script to blow fuses on already deployed parts based on VF curve from FAB.
  • Validated cryptographic implementation.
  • Owned validation of Reset and Security features on-die.
  • Wrote scripts to read on-die monitors/sensors and read register information.
  • Hands-on experience with FPGA and/or emulation platforms (Veloce, ZEBU).
  • Did Workload analysis and worked closely with performance team to update the existing fuse programming to improve boot and power related performance features.
  • I have also been part of RAS and Register Access Policy teams at AMD.
  • Validated complex security features.
  • Hands-on experience with x86 hardware debug, profiling, and trace.
  • Drive debug and resolution of MI GPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed.

Senior Researcher

University of British Columbia
09.2019 - 09.2020
  • Building multimodal models for biomedical datasets (CV+NLP).
  • Human body Pose Estimation: Pytorch + CNN (Generative AI).
  • Twitter Sentiment Analysis: LSTM + CNN + BERT.
  • Working on Biomedical research projects which involves Computer Vision.
  • I was involved in designing complicated Deep Learning models for biomedical dataset.
  • Comfortable with ML networks, frameworks, tools, and environments: Tensorflow, Pytorch.

Senior Researcher/Teaching Assistant

University of Cincinnati
01.2018 - 09.2019
  • I developed DL algorithms/models for biomedical data at Cincinnati Children's Hospital.
  • Experience in big data analytics with R/Python including statistical data modeling, manipulating and analyzing large datasets to extract useful insights for biomedical research.
  • Involved in building efficient KPIs of Language Model.
  • I worked as researcher building ML models for sensor data which helped to perform Gait Analysis.
  • I also worked part-time as Teaching Assistant for Embedded System Design. (Under-graduate and graduate)

SoC Front End Architect (Staff)

Samsung Corporation
05.2017 - 12.2017
  • I worked in Samsung research group worked closely with computer architects.
  • Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM IP.
  • Inserted DFT logic using design compiler.
  • Also, verified design features using VCS/waveform.
  • Experience Support and develop detailed implementation analysis and data-mining methodologies.
  • Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
  • I was part of CMOS Image sensor group.
  • Worked as Front end design engineer.
  • I was mainly part of hardware and software team.
  • Used Linux on regular basis in this role.
  • Performed micro-benchmarking at the RTL level for High performance SOC designs.
  • Comfortable with complex power management techniques.
  • GPU configuration/ GPU architecture level PPA estimation (via GPU test benches).
  • Wrote RTL extensively.
  • Comfortable with microarchitecture, synthesis and front end flows like CDC/RDC.
  • Worked extensively with Korean counterparts. I have worked in Korea for 6 months.

Sr Application Engineer (DC/DFTC)

Synopsys Corporation
09.2016 - 03.2017
  • Comfortable dealing with complex SoC issues and provide customer support.
  • Involved in developing Design Automation (CAD) tools which involved scripting in Python, ruby and TCL.
  • Supported Design Compiler, DFTC.
  • Can work under pressure.
  • Supported 3 clients - Samsung, Intel & Qualcomm.
  • Involved in debugging scripts and flows pertaining to PPA.
  • Have worked extensively with international counterparts from Israel, USA, India, Korea & Japan.

SoC Design Engineer & Product Development Engineer

Intel Corporation
01.2014 - 06.2016
  • I have been in 2 roles at Intel - SOC/IP Design Engineer & Product Development (Software Engineer).
  • Experienced in Siemens DFT tool, Scan compression and insertion, at-speed test, ATPG, fault simulation.
  • Gate level simulations with SDF.
  • Developed x86 test content to exercise new features and reproduce complex bugs in silicon.
  • Experience with ATE platforms - Advantest 93k
  • Worked extensively on RTL, synthesis, Front end flow, verification and bring-up.
  • Hands-on experience with FPGA and/or emulation platforms (Veloce, Palladium, ZEBU).
  • Experience in developing Sign-off methodologies such as Aging, STA, EM IR in advanced process nodes.
  • Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors.
  • Experience with hands-on debug in post-silicon environments using debug tools such as using ITP/JTAG, Logic Analyzers.
  • Work experience in Physical Implementation and Signoff methodologies.
  • Worked with design teams and customers on IP/SOC power projections, methodology alignment, use case analysis, max temp and power mitigations - Executing performance, perf /watt, perf / sq. mm modeling or analysis.
  • Presented architecture proposals and specifications to the design team; Communicated and articulated architecture proposals clearly and effectively across audiences ranging from hardware software engineers to architecture community peers, and to technology and business leadership.
  • Hands-on experience with silicon bring up of CPU or SOC products.
  • I comprehend SoC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power.
  • I worked cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
  • Post silicon support to ensure successful bring up.
  • Experience Strong front-end RTL engineering background.
  • Strong communications skills. Able to summarize complex problems for executive as well as drill down to details with architects and engineers.

RTL Design Engineer

Intel Corporation
12.2012 - 12.2013
  • Developed and implemented cutting-edge IP logic designs for Intel's CPU product.
  • Utilized industry-standard tools and methodologies to ensure high-quality chip designs.
  • Collaborated with cross-functional teams to understand product requirements and developed design specifications.
  • Performed design verification and validation to ensure functionality and reliability of designs.

Junior researcher

University of Cincinnati
09.2011 - 12.2012
  • Published thesis in OH tech consortium.
  • The research was for a period of 12 months. No salary.
  • Technology and Methods relevant for this job type (1) UVM & C++ for modelling. (2) SoC Front end design.

Embedded Software Engineer

TruBlu Technologies Limited
06.2009 - 06.2011
  • I worked in a startup as Embedded Software Engineer.
  • Comfortable with TCL, C++, SQL, Python coding.
  • I write programs/make data pipelines to stress test model's performance and scalability.

Education

MS - Computer Science (Data Science & ML)

University of Cincinnati
Cincinnati, OH
12.2019

MS - Computer Engineering (VLSI)

University of Cincinnati
Cincinnati, OH
12.2013

Electronics and Communication Engineering - undefined

Visvesvaraya Technological University
Belgaum, Karnataka
07.2010

Skills

  • Verification/Emulation
  • SoC Design
  • RTL & Front end & Verilog simulation tools
  • Gate-level simulations (SDF)
  • Experience with ATE platforms - Advantest 93k
  • Familiarity with UPF & CPF
  • automated test systems using laboratory equipment & software programming
  • DFT
  • Firmware Design

Personal Information

  • Date of Birth: 10/11/88
  • Nationality: Canadian

Timeline

Principal System Engineer

NXP
04.2023 - Current

Staff GPU Firmware/Embedded lead Engineer

AMD
06.2020 - 04.2023

Senior Researcher

University of British Columbia
09.2019 - 09.2020

Senior Researcher/Teaching Assistant

University of Cincinnati
01.2018 - 09.2019

SoC Front End Architect (Staff)

Samsung Corporation
05.2017 - 12.2017

Sr Application Engineer (DC/DFTC)

Synopsys Corporation
09.2016 - 03.2017

SoC Design Engineer & Product Development Engineer

Intel Corporation
01.2014 - 06.2016

RTL Design Engineer

Intel Corporation
12.2012 - 12.2013

Junior researcher

University of Cincinnati
09.2011 - 12.2012

Embedded Software Engineer

TruBlu Technologies Limited
06.2009 - 06.2011

MS - Computer Engineering (VLSI)

University of Cincinnati

Electronics and Communication Engineering - undefined

Visvesvaraya Technological University

MS - Computer Science (Data Science & ML)

University of Cincinnati

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