Applications Engineering Consultant | PowerPro | Power Analysis & Optimization
Overview
16
16
years of professional experience
Work History
Senior Applications Engineering Consultant
Siemens Digital Industries Software
Santa Clara, CA
01.2023 - Current
Leading PowerPro evaluations for North America customers, focusing on power optimization and estimation.
Owning and managing multiple customer accounts, driving adoption and long-term growth of PowerPro.
Collaborating closely with CAE and R&D teams to analyze and resolve complex customer issues.
Reviewing PRDs and specifications, influencing new feature development based on customer requirements.
Delivering technical demos and hands-on trainings for PowerPro.
Senior Product Applications Engineer
Synopsys Inc.
Sunnyvale, CA, USA
10.2020 - 01.2023
Supported PrimePower RTL as part of the Product Applications Engineering team, focusing on RTL-level power analysis and optimization.
Collaborated closely with R&D teams to validate new features by developing end-to-end test cases (design, simulation, synthesis, power analysis).
Partnered with worldwide CAE teams to analyze customer issues and drive new requirements evaluations.
Automated and improved the tool regression environment.
Developed technical presentations and training materials for internal teams and customers.
Senior ASIC Digital Design Engineer
Synopsys Inc.
Yerevan, Armenia
09.2010 - 10.2020
Led the development of a methodology for quick estimation of design metrics (area and power) for Synopsys DesignWare SMS IPs (Server, Processor, Wrapper, ECC compilers) used in embedded memory test solutions (MBIST).
Conducted in-depth analysis of parameterized RTL architectures, enabling scalable evaluation across multiple MBIST configurations.
Performed logic synthesis across diverse configurations to characterize area trends.
Executed static and dynamic power analysis, building comprehensive datasets for accurate power modeling.
Designed and implemented TCL-based estimation frameworks using least squares regression to enable fast and reliable early-stage area and power predictions.
Developed a machine learning–based estimation tool that significantly improved prediction accuracy and reduced dependency on full synthesis and power flows.
Collaborated cross-functionally with software engineering teams to integrate estimation capabilities into the Synopsys DesignWare SMS STAR Planner tool, enabling early design planning and faster decision-making.
Developed PnR flow for Synopsys DesignWare SMS IP considering low power design techniques (UPF).
EDA Interoperability Verification Engineer
Virage Logic Inc.
Yerevan, Armenia
03.2010 - 09.2010
Analyzed parameterized MBIST RTL designs.
Developed knowledge of the MBIST design flow.
Education
PhD - Computer Engineering
Institute for Informatics and Automation Problems of NAS RA
01-2019
PhD Student, Research Scientist - Computer Systems and Informatics
National Polytechnic University of Armenia
01-2012
Master’s Degree - Informatics and Computer Science
National Polytechnic University of Armenia
01-2009
Bachelor’s Degree - Computers, Computer Complexes and Networks
National Polytechnic University of Armenia
01-2007
Skills
Power Optimization & Estimation
Expert in RTL power optimization and estimation (PowerPro, PrimePower RTL)
Strong experience in PPA (Power, Performance, Area) analysis at RTL level
ASIC Design & Methodologies
Solid understanding of ASIC design flow (RTL → GDS)
Strong knowledge of MBIST design flows
Good understanding of computer architecture
EDA Tools
PrimePower RTL, PowerPro, Veloce, VCS, Design Compiler, PrimeTime, PrimeTime PX, Formality, IC Compiler, IC Compiler II, Fusion Compiler, Library Compiler, RTL Architect, Embed-It tools
L. Martirosyan, “Machine learning application for the memory BIST network design characteristics estimation”, Proceedings of the NAS RA and SEUA: Technical Sciences, Yerevan, Armenia, 2018.-Vol. 71. N4, pp. 495-502.
L. Martirosyan, “Easy to Use Evaluation of Quality Characteristics for a Hierarchy of RTL Compilers”, East-West Design & Test Symposium (EWDTS), Novi Sad, Serbia, 29 Sept.-2 Oct. 2017, pp. 430-434, IEEE Xplore: 16 November 2017.
L. Martirosyan, “The Quality Characteristics Estimation Methodology for the Nanoscale RTL Compilers”, Proceedings of the NAS RA and SEUA: Technical Sciences, 70. N2, pp. 218-226, Yerevan, Armenia, 2017.
L. Martirosyan, “A Quality Characteristics Estimation Methodology for the Hierarchy of RTL Compilers”, East-West Design & Test Symposium (EWDTS), Yerevan, Armenia, 14-17 Oct. 2016, pp. 68-71, IEEE Xplore: 09 January 20.
L. Martirosyan, G. Harutyunyan, S. Shoukourian, Y. Zorian “A Power Based Memory BIST Grouping Methodology”, East-West Design & Test Symposium (EWDTS), Batumi, Georgia, 26-29 Sept. 2015, pp. 27-31, IEEE Xplore: 16 June 2016.
L. Martirosyan, “A Quick Power Consumption Estimation Method for RTL Compilers”, Computer Science and Information Technologies (CSIT), Yerevan, Armenia, IEEE Xplore: 16 January 2014.
L. Martirosyan, “A Quick Area Estimation Method for RTL Compilers”, Proceedings of the NAS RA and SEUA, Yerevan, Vol. 65 (3), pp. 287-294, ISSN 0002-306X, 2012.
Timeline
Senior Applications Engineering Consultant
Siemens Digital Industries Software
01.2023 - Current
Senior Product Applications Engineer
Synopsys Inc.
10.2020 - 01.2023
Senior ASIC Digital Design Engineer
Synopsys Inc.
09.2010 - 10.2020
EDA Interoperability Verification Engineer
Virage Logic Inc.
03.2010 - 09.2010
PhD Student, Research Scientist - Computer Systems and Informatics
National Polytechnic University of Armenia
Master’s Degree - Informatics and Computer Science
National Polytechnic University of Armenia
Bachelor’s Degree - Computers, Computer Complexes and Networks
National Polytechnic University of Armenia
PhD - Computer Engineering
Institute for Informatics and Automation Problems of NAS RA