Summary
Overview
Work History
Education
Skills
Projects
Awards
Additional Information
Websites
Timeline
Generic
Mark D Bellows

Mark D Bellows

Hillsboro,OR

Summary

Experienced Computer Hardware Verification/Validation Enginer with extensive experience with internal and external subsystems.

Overview

30
30
years of professional experience

Work History

System Validation Engineer

Intel Corporation
Hillsboro, OR
09.2014 - Current
  • Validated SOC with Synthetic & Traditional content increasing coverage
  • Operating System Validation using off-the-shelf applications
  • Established Synthetic Validation using internal and external applications and methods - finding 8 hardware bugs in 10 weeks
  • System Bring-up using software and hardware to debug issues in record breaking time of 4 weeks
  • Tested concurrency and functionality of many units: GPU, CPU, Memory ( DDR3,DDR4, LPDDR4 ) IPU, GMD
  • Field support of debug critical customer issues isolating critical bug at low temperatures
  • Found and Triaged power management bugs
  • Leading teams - across geographies - India, Malaysia, Israel
  • Proved successful working within tight deadlines and fast-paced atmosphere
  • Monitored and maintained engineering disk space reducing wasted space by 10%
  • Created and established methods to detect and reduce defects from previous known problems (BEAT) to improve overall project quality

Advisory Engineer

International Business Machines
Rochester, MN
09.1992 - 04.2014
  • DDR3/DDR5 memory controller validation for proper function
  • Virtual system modeling of future systems to improve quality
  • Silicon Bring-up, lab tool for p/i/z Series
  • Flash memory testing for SSD retention and survivability
  • Verification of PCI - for correct function and no failures in customer product
  • Power Reduction - ESD survivability analysis - feeding back predicted failure mechanism for robust design
  • Created XDR Memory (Rambus) design, debug and future capabilities
  • Network Processor Design - congestion control for reliability and function
  • Memory Controller Design for PS3 (Sony/Toshiba/IBM) creating fastest console in market at that time
  • Cache/Coherency controller validation for bug removal
  • 32/64Bit FPU validation - root causing problems in calculations, flows , optimizations and internal checkers

Education

Masters of Science EE -

University of Minnesota
Minneapolis, MN
06.1999

Bachelors of Science - EE, Electrical And Computer Engineering, Mathematics

Brigham Young University
Provo, UT

Skills

  • Debug of SW/HW
  • Cross-Functional Team Leadership
  • Developing / Implementing Tests
  • Training / Mentoring / Helping
  • C, perl, python VHDL, Verilog, FPGA programming
  • Linux, Unix, AIX, Windows
  • Organizer - staff & technical
  • Innovator - solves problems using automation

Projects

 Meteorlake (14 Gen)— Synthetic Validation Lead (North)

Intel Consumer processor validated with new content, validating 8 different IPs, developing novel testing methods

TigerLake/Broxton — Memory Validation Intel Consumer and Devices Processors - verifying memory controllers and subsystems.

i/p/zSeries PowerPC NorthStar/Muskie - cache controller validation-verification, memory controller design, network processor design, floating point unit verification


Awards

 US Patents 22 filed in the areas of Memory and Networking

First Synthetic GMD Tests developed and integrated two different methodologies

Presidential Volunteer Service Award hundreds of hours with city youth mentoring and LEGO robotic training.

Additional Information

  • Toastmasters (ACB,ALB)
  • B.S.A. Wood Badge

Timeline

System Validation Engineer

Intel Corporation
09.2014 - Current

Advisory Engineer

International Business Machines
09.1992 - 04.2014

Masters of Science EE -

University of Minnesota

Bachelors of Science - EE, Electrical And Computer Engineering, Mathematics

Brigham Young University
Mark D Bellows