Summary
Overview
Work History
Education
Skills
Timeline
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Masa Higashitani

Masa Higashitani

Summary

With over 35 years of experience in the semiconductor industry, successfully driving numerous projects from inception to final product. Expertise in DRAM, NOR Flash Memory, 2D-NAND & 3D-NAND Flash memory devices, process integration, and reliability. Proven track record of driving new technology development, including Wafer-Wafer Bonding technology, MLC operation, New Memory Architecture (LLF: Low Latency Flash), Analog Memory, and more. Possess the ability to effectively coordinate business requirements with technical challenges for seamless alignment. Excelled in coordinating and interfacing among design, device, process, and package teams throughout career. Extensive experience in engaging businesses in technology development and transfer, as well as product manufacture. Involved in numerous joint-venture projects between Japanese semiconductor companies and US-based organizations. Excellent interpersonal and teamwork skills, along with strong problem-solving techniques and innovative ideas. Contributed to the creation of over 200 patents.

Overview

36
36
years of professional experience
1989
1989
years of post-secondary education

Work History

Senior Vice President of Technical Engineering

Western Digital
07.2021 - Current
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • Lead overall 3D- NAND Development
  • Make technical judgments (New Idea: Wafer-Bonding technology, On-Pitch SGD formation, New operation scheme, etc.)
  • Define Chip architecture
  • I/O scheme, Power usage, Cell reliability (Coordinate these items with Business Unit)
  • Technology transfer work for ~300Layer 3D-NAND
  • Coordinate Business Unit requirement and technical challenges (I/O, Cell reliability, Cell performance)
  • Establish technology transfer team as scheme for Technology Ramp
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Vice President of Advanced Process and Device

Western Digital
09.2016 - 06.2021
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 3D-NAND Development (128Layers, 160laters and ~218layers)
  • Drive CBA technology for 218Layers 3D-NAND, Lead 128Layer Development
  • Define QLC chip architecture
  • Cell operation (Read scheme), Cell Reliability, I/O scheme
  • Drive QLC device - Bring new process method for 3D NAND cell
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Senior Director/ Director/Principal Engineer

Western Digital
02.2001 - 08.2016
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 3D-NAND 96Layers Development & Transfer to Mass Production
  • Lead 96layers Development - Drive New Process (Related Memory Hole)
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Senior Director/ Director/Principal Engineer

Western Digital
01.2013 - 01.2015
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 1Znm NAND development (Z is number from 0 to 9 and beyond)
  • Lead 1Znm NAND device development - Manage Business requirement
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Senior Director/ Director/Principal Engineer

Western Digital
01.2013 - 01.2014
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 3D-NAND 64Layers Development & Transfer to Mass Production
  • Lead 64Layers Development - Establish 3D-NAND Mass production
  • (Inspection, Defect management)
  • Drive 3D-NAND reliability evaluation - (One example, I drive Memory Hole RIE scheme.)
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Senior Director/ Director/Principal Engineer

Western Digital
01.2011 - 01.2013
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 1Ynm NAND development (Y is number from 0 to 9 and beyond)
  • Manage NAND cell design from device operations (Program, Erase, Read, Verify)
  • Manage PDK (Example, I drive STI Air-gap)
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Senior Director/ Director/Principal Engineer

Western Digital
01.2001 - 01.2011
  • Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
  • 19nm/24nm/32nm/ 43nm (1st 4 bits/cell NAND chip in the world)/55nm /70nm/90nm/0.13um/0.16um 2D NAND development
  • Making TEST CHIP, -PDK/CMOS/Transistor Model
  • Process flow, Device operation (MLC function)
  • (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)

Project Manager

Fujitsu
01.1997 - 01.2001
  • Company Overview: (Worked at AMD Sunnyvale during 1997~2001)
  • 0.18um/0.25um/0.35 NAND Flash memory project manager (Assignee at AMD)
  • Created Process flow, EDR and GDR
  • Designed test chip, running test chip silicon
  • Transferred 0.25um NAND flash memory technology to manufacturing FAB (FASL: Fujitsu AMD Semiconductor Limited) for mass production
  • Established baseline D/S flow and Repair scheme
  • (Worked at AMD Sunnyvale during 1997~2001)

Project Sub Leader

Fujitsu
01.1992 - 01.1996
  • 0.35um/0.50um NOR flash memory project sub leader
  • Established 8-inch wafer flash memory process development (Establish Isolation process, Well formation, Self-Align-Source, etc.)
  • Transferred 0.35/0.50um NOR flash technologies to FASL for mass production Characterized NOR flash memory product and device reliability
  • Working on Analogy Memory architecture with NOR Array Test Chip

Project Sub Leader

Fujitsu
01.1989 - 01.1992
  • 0.35um DRAM project sub leader
  • Test Chip making/Transistor modeling/Engage Phase-shift-Mask technology for DRAM Contributed EDR, GDR and Process flow

Education

MS - Physics

KANAZAWA UNIVERSITY

BS - Physics

YAMAGATA UNIVERSITY

Skills

UNIX

Timeline

Senior Vice President of Technical Engineering

Western Digital
07.2021 - Current

Vice President of Advanced Process and Device

Western Digital
09.2016 - 06.2021

Senior Director/ Director/Principal Engineer

Western Digital
01.2013 - 01.2015

Senior Director/ Director/Principal Engineer

Western Digital
01.2013 - 01.2014

Senior Director/ Director/Principal Engineer

Western Digital
01.2011 - 01.2013

Senior Director/ Director/Principal Engineer

Western Digital
02.2001 - 08.2016

Senior Director/ Director/Principal Engineer

Western Digital
01.2001 - 01.2011

Project Manager

Fujitsu
01.1997 - 01.2001

Project Sub Leader

Fujitsu
01.1992 - 01.1996

Project Sub Leader

Fujitsu
01.1989 - 01.1992

BS - Physics

YAMAGATA UNIVERSITY

MS - Physics

KANAZAWA UNIVERSITY
Masa Higashitani