Mohamed Sayed Ali Ali Shehata

In addition to my previous role as Sr. QA Engineer I:

• Delivered technical guidance to team members, boosting skills and operational efficiency.
• Contributed to formation and training of QA team, ensuring effective follow-up operations.
• Reviewed and approved project test plans, test cases, and automation scripts for quality assurance.
• Analyzed test results, isolated defects, and collaborated with Product and R&D teams for prompt resolution and increase code coverage.
• Supported PDK enablement on customer site for advanced technology nodes like TSMC N2, N3, N5 and GF12.

• Collaborated with development and product engineering teams to formulate test and quality plans for each release.
• Created, executed, and maintained regression test suites to ensure software reliability.
• Analysed regression failures and updated test cases to enhance accuracy.
• Measured test coverage and implemented additional test cases to improve outcomes.
• Automated test cases for defects reported by customers to streamline testing processes.

• Responsible for overseeing all activities within team.
• Deciding how to approach tasks and develop plan to accomplish them.
• Distributing information and tasks to team members and stakeholders.
• Keeping track of and structuring various tasks, employees and documents.
• Determining goals that members will work toward.
• Continuing PEM role in SerDes USB2 product line in Synopsys.

• In addition to Staff CAD responsibilities, leading CAD team at Si-Vision.
• Prepare technical exams and interviews for CAD team members.
• Prepare, execute training plans for new CAD engineers.
• Do regular performance evaluation.
• Provide CAD help and consultation when needed.
• Discover training needs and provide coaching
• Acting as Project Engineering Manager (PEM) for different Synopsys IPs like Bluetooth, SerDes.
• Participate and review SOW.
• Prepare project plans and review deadlines with R&D teams.
• Coordinate between teams, follow up on milestones, and managing project risk
• Prepare final IP package and deliver it to release QA team.
• Communicate any issues in IP packages to concerned team.

• Work closely with IC design teams throughout design cycle to develop and maintain projects' work areas.
• Support test and release of combinations of internal and third-party software used by R&D designers.
• Develop and support Analog/Mixed Signal IC simulation methodologies and framework.
• Create relevant documentation, testcases and prioritize issues following departments processes.
• Handle design workspace using version control systems.
• Responsible for CAD development for Synopsys, Cadence and Mentor tools.
• Interface with other groups, for example PDK, IT & EDA vendors, as needed to assist in enhancing design productivity and improving overall framework.
• Develop and apply CAD software engineering methods, theories, and research techniques in investigation and solution of technical problems.
• Write scripts to automate IC design activities using Shell, Tcl, and Perl.
• Provide prompt advices, recommendations and resolutions for designers while using design flow.
• Participate in quality management system and applying ISO9001:2015 quality standard in CAD team and participated in internal quality audit.
• Responsible for different Synopsys tools’ installation as part of Si-Vision learning academy for students.
• Supervise and guide university students in their graduation project.

• Wrote scripts to automate testing activities using Shell and SVRF.
• Participated in test plan and quality plan definition of each release in coordination with development and marketing teams.
• Created, ran, and maintained regression test suits.
• Analyzed regression failures and updated test cases.
• Measured test coverage and implemented new test cases to improve it.
• Analyzed defects reported by customers and automated their test cases.

• Wrote some use cases for Visual Diff project.
• Wrote functional specifications for congestion maps and Visual Diff projects.
• Developed Graphical User Interface (GUI) using Qt, AMPLE, and C++ for several products and different projects like:
• Pyxis Custom Router (PCR): Congestion Maps, Hierarchal DFM, and DRC stepper.
• Visual Diff.
• Participated with ideas and suggestions in GUI developing.
• Participated in development of EDIF converter project.

• Did research on Electrical Physical Reconciliation project (EPR).
• Handled several customer requests to solve and/or enhance GUI of Pyxis Custom Router.
• Developed Mentor Process Design Kits (PDKs), both front and back ends, of several foundries like:.
• Global Foundries, On-Semi, UMC, and TSMC.
• Wrote AMPLE callbacks functions and AMPLE code to generate Parameterized Cells (PCells) which are used within layout editors.
• Wrote and edit Netlist Control Files (NCFs).
• Wrote needed shell and AMPLE scripts to facilitate PDKs development.
• Ran PDKs qualification tests like Design Rule Check (DRC) and Layout Versus Schematic (LVS).
• Added Mentor specific enhancements (like DFM Vias) to TSMC iPDKs.

• Embedded RF remote control system.
• Design and implement both transmitter and receiver circuits.
• Use Micro controller to control transmission and reception of data.