Hardware Design Engineer with 5+ years (3+ industry) in RTL design, SoC microarchitecture, memory subsystems (SRAM/ECC/Cache), and ASIC design flow including synthesis, STA/CDC, UVM verification, and timing closure. Industry experience at NVIDIA (Tegra TB-500) and Synopsys in RTL implementation for graphics/AI SoCs supporting DDR-like protocols via AXI/APB.
Hi, I’m
Muhammed Kawser Ahmed
Gainesville,USA
Summary
Overview
5
years of professional experience
Work History
University of Florida
Graduate Research Assistant
01.2021 - Current
Job overview
- Lead researcher on power-isolated FPGA/SoC frameworks for multi-tenant and safety-critical designs.
- Architected and verified an FPGA-based multi-power-domain isolation framework for secure, multi-tenant SoC environments targeting a 28 nm implementation. Defined hierarchical power intent (UPF) for dynamic domain partitioning and performed low-power verification using static and simulation-based checks. Developed comprehensive SystemVerilog/UVM-style testbenches and test plans to validate power-domain switching, isolation cell functionality, and reconfiguration correctness under variable voltage and frequency conditions. Conducted extensive functional and fault-injection simulations to evaluate trade-offs in area, IR-drop, power delivery integrity, and reconfiguration latency. Executed Vivado/Cadence STA on multi-power-domain isolation framework, verifying CDC paths for secure memory controllers.
- Designed and verified RTL/SystemC subsystems for the Fine-Grained Physical Isolation Framework (FPIF), which includes isolation controllers, secure configuration decoders, and protected BRAM partitions. Implemented power-optimized architectures using clock gating, operand isolation, and multi-voltage domain techniques to minimize dynamic power. Designed unified verification environments with directed, constrained random and power-aware test suites to validate functionality in multiple power and timing scenarios. Correlated SystemC and RTL models through coverage-driven verification, ensuring bit-accurate alignment and consistency across functional and architectural abstraction levels.
- Executed full timing and power closure for the FPIF design using Cadence Tempus and Vivado static timing analysis (STA) tools. Power intent validation (UPF) was performed to ensure proper insertion of isolation cells, placement of level shifters, and retention strategies in power domains. Applied regression-based timing verification, switching activity analysis, and gate-level power estimation (PrimePower/Innovus) to validate low-power operation, leakage reduction, and voltage scaling efficacy prior to tapeout.
NVIDIA CORPORATION
Tegra SoC Engineer Intern
05.2024 - 12.2024
Job overview
- Designed power-aware automation and safety infrastructure for Tegra TB-500 SoC integration
- Created Python/IP-XACT automation for memory controller metadata translation to synthesizable RTL/SystemC, enabling SoC integration, CDC/reset checks, and downstream STA/timing analysis on Tegra TB-500.
- Supported Global Interface (GI) blocks replacing aggregators; automated clock/reset/AXI connections for memory subsystems, reducing manual RTL edits.
- Worked on analyzing cross-domain signals between IP blocks running on different clocks and identifying where synchronizers or FIFOs were required to ensure safe data transfer. Analyzed CDC paths and reset consistency across IP blocks for Tegra TB-500 using Synopsys tools, ensuring safe data transfer in multi-clock domains.
- In a second project, a chip safety traceability system was co-developed linking design deliverables to ISO 26262 / IEC 61508 rules, automating power-state dependency checks, with traceability for memory controller compliance. Implemented using JavaScript, TypeScript, and Node.js, the flow suggested applicable safety rules based on chip metadata and integrated with JAMA, enabling users to track requirement changes and maintain consistency between teams.
- 3.5 years Professional | 1 year internship | 5 year research experience
Synopsys INC.
TRoot Processor Engineer Intern
06.2022 - 12.2022
Job overview
- Contributed to secure SoC IP development and formal verification at RTL and firmware levels.
- Designed and implemented parameterized RTL modules for the TRoot Secure Processor product line, including a Firewall, Bus Monitor, and Obfuscation IP, following detailed microarchitecture specifications. Integrated secure transaction handling and processor-level control to improve configurability and reuse across multiple IP blocks. The wrappers were connected to the AXI-Lite and APB interfaces, enabling seamless integration into SoC subsystems.
- Integrated clock domain crossing (CDC) logic to ensure reliable operation across asynchronous domains, since crypto cores operated on separate secure clocks. Validated the CDC logic using Synopsys lint and CDC tools, identifying and correcting crossing issues prior to synthesis targeting reduction of late-stage design errors and improved timing closure.
- Built ATFG-compatible RTL firewalls with scan insertion (JasperGold) and CDC logic for secure processors, achieving timing closure on AXI/APB memory paths.
Education
University of FloridaUSA
PhD from Electrical and Computer Engineering
07.2025
University Overview
University of FloridaUSA
Masters from Electrical and Computer Engineering
04.2023
University Overview
Shahjalal University of Science and TechnologyBangladesh
BSc from Electrical and Electronics Engineering
01.2018
University Overview
Teaching Assistant | Computer Architecture, System-on-Chip (SoC), SystemC modeling and UVM | 2022 - 2025
Skills
- C C Python SystemVerilog SystemC Verilog UVM RTL Design IP-XACT VCS Vivado HLS Verdi Cadence Innovus Virtuoso Genus ModelSim TCL Makefile Github Perforce PSL Perl LTSprice Altium Designer VC-Formal PrimeTime Scan insertion (Jasper Gold) UEFI Trusted Execution TPM/Measured Boot Confidential Computing PetaLinux Typescript React JavaScriptMemory Design: SRAM/ECC Controllers Cache Coherence (MESI) AXI/APB for DRAM Interfaces
Accomplishments
Accomplishments
- Received prestigious J. Margaret A. Ross Fellowship for outstanding academic achievements for Summer 2025 semester in UF.
- Stood 3rd (Gold, 1st) (2015) in Inter University National Robotic Competition, Bangladesh.
- Stood 2nd (Silver, 2nd) (2018) in Inter University National Robotic Competition, Bangladesh.
- Received Grade A (Out of A+) at Training Institute of Chemical Industries (TICI), Ghorashal, Gazipur in Sep 2017
Timeline
Tegra SoC Engineer Intern
NVIDIA CORPORATION
05.2024 - 12.2024
TRoot Processor Engineer Intern
Synopsys INC.
06.2022 - 12.2022
Graduate Research Assistant
University of Florida
01.2021 - Current
University of Florida
Masters from Electrical and Computer Engineering
Shahjalal University of Science and Technology
BSc from Electrical and Electronics Engineering
University of Florida
PhD from Electrical and Computer Engineering