Naveen Kumar Reddy Beerelly

Silicon Validation Engineer with experience in SoC validation, content conversion, DFT for HVM, content validation on ATE testers, Test programs, reject and failure analysis with focus on USB, PCIE IPs and CMT, HDMT testers.

GPGPU implementation of Connected Component Algorithm

• Used CUDA to implement 4 connectivity 2-pass connected component algorithm
• Executed code on Fermi GTX-480 Nvidia GPU
• 2x performance improvement was achieved compared to a very fast sequential algorithm

Cache Performance Improvement

• Modified the source code of Multi2sim to achieve non-inclusive cache performance with inclusive caches
• Used Query Based Selection (QBS) as cache replacement policy
• Achieved 20% IPC performance improvement with SPEC 2006 benchmarks

RTL design of 16 bit Vector Processor

• RTL implementation of a Vector Processor with a data-path consisting of 8 entry scalar register file, 8 entry vector register file, half precision floating point adder and multiplier
• Implemented Vector chaining and Strip-mining
• Synthesized the Verilog code using Design compiler and ran fault coverage simulations & ATPG using Tetramax

ASIC Design of 128kb (2k x 64b) SRAM Array

• Designed the layout of a 128Kb SRAM operating at 650MHz in Cadence Virtuoso
• Employed Sleep Transistor Circuit to reduce sub-threshold leakage power consumption
• Used Cadence SKILL Script to replicate 6T SRAM cells to form an array in layout

Design of 16-bit Brent Kung Adder

• Designed the layout of Brent Kung parallel prefix adder operating at 800MHz, 110oC, 1.1V VDD in Cadence Virtuoso
• Optimized the design to obtain low power consumption
• Used 45nm Free PDK and HSPICE for simulations

• Naveen Kumar Reddy Beerelly, Chandrasekhar Mummidi, V Sri Hari, M.B Srinivas, “A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units” in IEEE proc., 2014, 27th International Conference on VLSI Design