RICHARD DUMENE
Dallas,TX
Summary
Driven and passionate test expert recognized as a thought leader in the industry. Regularly engages with internal senior management and external vendor leadership to drive test innovation. Extensive expertise in defining and implementing sweeping and fundamental change across a large semiconductor corporation. Cultivated a broad network of industry contacts and relationships, enhancing the ability to make a significant impact in the field.
Overview
10
10
years of professional experience
Work History
Principal Test Architect
Renesas Electronics
04.2023 - Current
- Report to Sr Director of Test and SiV for largest division within Power Product Group
- Responsible for building and leading test architecture team, responsible for defining test roadmap, requirements, DFT, test program robustness, checkout, and spec compliance
- Created and defined company wide ATE and hander roadmap Creation and update process
- Completely re-scoped company wide ATE roadmap, driving from over 200 active configs of ATE to less than 10
- Conducted broad paper studies of all available ATE platforms and down selected to 5 configurations for all of Renesas Power Business
- Engaged with vendors to complete both paper studies and online proof of concept solutions to validate roadmap selection process
- Drove new roadmap instrumentation and capability for multiple vendors
- Defined company wide TE development flow and deliverables in new consolidated development process
- Engage with internal operations team in both broad weekly execution meetings and 1-1 conversations to ensure critical project progress
- Ersatz manager for top TEs in group, task and deploy tiger team of test engineers for critical projects
- Manage > 1 M in annual hardware spend and > 10 / year tester purchases
- General chair for Semicon West Test Vision 2024
- Responsible for gathering information for and primary contribution to HIR-AMS test roadmap chapter
- Developed integrated test solution with vendor for turret based functional test
- Create and manage libraries for test development
- Responsible for critical projects including pipecleaners for new roadmap testers and most critical projects for Power Product Group
TEST ENGINEER (Member Group Technical Staff)
TEXAS INSTRUMENTS
05.2015 - 04.2023
- Elected Member of the Group Technical Staff (MGTS)
- Operated as technical lead for test engineer team
- Worked with management to develop roadmaps and define test strategies to lower cost without compromising quality
- Drove innovation across business unit in terms of test strategy and platform
- Evaluated various ATE platforms for competitiveness
- Lead for high power automotive isolated gate driver, senior TE on project leading team of 4 engineers
- Developed and defined test flow, led test hardware design, drove > 75% cost reduction over previous generation, record speed debug
- Vice General Chair for Semicon West Test Vision 2023, Program Committee Chair for Semicon West Test Vision 2022, hosted panel for Test Vision 2021
- Defined and developed automated test data analysis flow for new program release regression prevention and compliance enforcement
- Defined and developed a large-scale data management tool, used ATE project as the pilot project for this tool, storing all data collected through NPD process, currently one of the owners of this tool
- Co-authored a guidebook to managing test naming conventions to leverage internal tools for powerful and fast data analysis and self-documentation of datalogs and more robust creation of test plans, led project to implement this into a new workflow to automatically generate limits sheets from test plan
- Presented at TI Technical Leadership Conference 2019 and 2022
- Helped develop automated spike check system and Test Point Interposers, successfully created first TPI for strip solution at TI
- Product line wide audit and improvement of abs max testing and OVST test conditions, reduced DPPM on problem parts by over 40%
GRADUATE RA AND GTA
VIRGINIA TECH
01.2017 - 01.2018
- Conducted research on additively manufactured RF structures (X-Band)
- Taught Undergraduate Electronics Lab, Top Rated TA in ECE department twice
Education
BS - ELECTRICAL ENGINEERING
VIRGINIA TECH
BLACKSBURG, VAMS - ELECTRICAL ENGINEERING
VIRGINIA TECH
BLACKSBURG, VA01.2018
Skills
- Strategic Vendor Engagement
- Executive Presentations
- Purchasing Negotiation
- Ultra-High Voltage Test
- Isolation Test
- High Current Test (>100A)
- GaN/SiC
- Automotive
- AEC-Q100/Q101
- ASIL-D
- Low Noise Circuit Design
- ETS 88/364/800
- IGXL
- STS-8300
- DMDx / DxV / Unison
- V93k
- PMIC
- Buck/Boost
- LDO
- C
- Unix Scripting
- Git
- SVN
- CI
- Data Analysis
- High-Speed Debug
- Defect Acceleration
- Developing Training Docs
Timeline
Principal Test Architect
Renesas Electronics
04.2023 - Current
GRADUATE RA AND GTA
VIRGINIA TECH
01.2017 - 01.2018
TEST ENGINEER (Member Group Technical Staff)
TEXAS INSTRUMENTS
05.2015 - 04.2023
MS - ELECTRICAL ENGINEERING
VIRGINIA TECH
BS - ELECTRICAL ENGINEERING
VIRGINIA TECH
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