Open To Work
Verified
This profile is verified using an email address.
Richard Petranovich
Mask Layout designer
Maricopa,USA
Summary
Experienced IC Layout CAD Designer with 20+ years extensive knowledge in full custom analog and digital mixed signal IC layout design currently working in 6nm, 12nm and 16nm finfet technology. Senior Maintenance and Industrial Engineer with extensive facility equipment and electronic repair experience. Extensive knowledge of OSHA safety and production standards in a Hazardous Semiconductor environment, trained in HASMAT, SCBA, lock out, Tag out. Certified Emergency response team leader and coordinator with Chandler Fire Department. Ability to function effectively in a team-oriented environment while handling multiple priorities at a fast pace. Worked with many vendor equipment companies on systems upgrades, and process enhancements for more robust machines. Trained junior level technicians. Strategic thinker with effective analytical, organizational, and leadership skills. Experienced in all phases of electronic troubleshooting and electromechanical repair, and chemical handling systems. Strong technical solving skills, close attention to detail, flexibility, team player with good work ethics.
Overview
39
39
years of professional experience
Work History
Principal Layout designer
Microchip Technology
Chandler, AZ
12.2022 - 06.2026
- Analog mask layout designer, NCS high speed transceivers Dept. Work consists of designing macro's used in larger chip structures. Special attention to analog requirements, critical nets such as differential pairs, and high-level matching techniques for performance matching using common centroid and matching connection points creating symmetry. Creating wells and channels to surround devices for power and bias backgates. Started working in 28nm TSMC geometry projects currently working in finfet 6nm,12nm and 16nm. Enhanced and robust layout beyond minimum drc requirements to create first pass devices with high yield. Used Cadence Virtuoso in the 28nm projects, currently using Pegasus for running drc and lvs checks in the 12nm finfet process.
Mask Design Engineer
Intel Corporation
Remote
03.2021 - 08.2022
- Cad II QA engineer Working for inlet as a Contingent Worker, Running of various checks to verify integrity of finfet 3nm P-cells for test case library applications. Unix and synopsis-based verification tools and cadence. Ensuring accurate and quality assurance for standard use library cells.
Mask Layout Engineer Contractor
Qualcomm, Inc.
Raleigh, NC
12.2014 - 04.2016
- Designed custom layouts of memory arrays/caches in TSMC 28nm deep submicron CMOS process technology. Project consisted of memory design, read write signals, shift registers, precharge and charge pumps and critical matching of components and clock routing. Design was done using most current version of Cadence Virtuoso XL and cutting-edge internal technology along with Tass device placement. Responsible for verifying completed layouts are design rule and schematics versus Layout correct using Calibre DRC/LVS verification tools. Floor planned top level placement of memory arrays with cross signals. During this time, I completed several arrays and cells, no top-level tape-out required for this position, but schedules were planned and met.
Analog IC Layout Designer Contractor
Cirrus Logic, Inc.
Tucson, AZ
09.2013 - 08.2014
- Short term critical tape-out assignment designing custom layouts for CMOS circuitry in TSMC 65nm deep trench process technology. Project consisted of ION design for amplifier circuit, requiring trench isolation and critical matching of components. Design was done using standard Cadence Virtuoso not XL, devices were instanced in, and net list had to be manually loaded and updated. Responsible for verifying completed layouts are design rule and schematics versus Layout correct using Calibre DRC/LVS verification tools Floor planned top level placement of amplifier cell. During this time, I assisted in completion of 1 tapped-out Mixed-Signal ICS.
Hydole Power Electronics Hardware Engineer
Freescale Corp.
Tempe, AZ
10.2010 - 08.2013
- Development of Hybrid electric vehicles includes inverters, chargers, DC/DC converters, High power, High voltage, switch-mode power supplies. Responsible for high power rack 600-volt, 600 amp, running hardware and software tests using interface boards, Lab View for monitoring tests and presentation of data collected. Design components and hardware assemblies using Solid works CAD design. Trained in Eagle CAD schematic capture and pcb board layout. Facilitating chiller units to inverter and power rack for cooling and wiring of test equipment. LabVIEW interface. Running common Lab equipment, Oscilloscopes, curve tracers, spectrum analyzers, true RMS meters, soldering equipment, Variac voltage supply, lab maintenance, ordering equipment and supplies. Writing test reports, assembly, and repair of PCBs. Controlling and maintaining design specs in internal system. Member of the Freescale Emergency response team.
Mask Layout Engineer
Freescale Corp.
Tempe, AZ
11.2007 - 02.2010
- Analog layout of Smartmos 8mv, and 8lv process technology. Supported Sensor, Consumer and Automotive groups. Recent responsibilities have been making layout improvements to prevent ILD cracking issues in circuits which involves working closely with fab engineers. Circuit design using best layout and matching techniques. Floor planning, and power routing to ESD and Pad structures. Design lead on several projects and have tapped out several chips. Strong communication skills with design engineers, project coordinators, assigning Layout resources, and meeting tape-out schedules.
Mask Layout Engineer
Infineon/Qimonda RTP Design Center
Cary, NC
05.2005 - 10.2007
- Custom Mixed Signal Analog and Digital design for 1GT70 memory devices, involves design of circuits within a spine infrastructure with octants and arrays using deep trench technology. Top level floor planning and resource management. Responsibilities include P-cell layout to top level hookup. DRC and LVS verification. Responsible for several reports, scheduling layout resources, and training junior layout personnel.
Analog IC Layout Designer-Contractor
Intersil Corporation, Seattle Design Center
Kent, WA
01.2004 - 02.2005
- Layout designer for the notebook application design group, involving design of standard P- cell to top level, tape-out and verification of complex high performance analog circuits. Utilizing analog techniques in .6um IBM architecture that includes common centroid, matching, symmetrical layout and timing, balancing of circuits, antenna checks and noise isolation. Floor planning and streaming data to external foundries. This position required strong communication skills, and meeting tape-out deadlines.
Layout Design-Engineer
Virage Logic Corporation, Seattle Design Center
Bellevue, WA
09.2001 - 05.2003
- Layout design on non-volatile embedded memory in a standard .18um, .13um, and.09um CMOS (SOC) process. Used TSMC discrete architecture to develop programmable memory compilers. Unix based system requiring compiling of instances and framework, developing global center and I/O structure. Completed task of converting entire .18um layouts to .13um in standard library and existing cells and instances.
Senior Diffusion/Etch Engineer
Microchip Corp
Chandler, AZ
01.2000 - 08.2001
- Responsible for C- shift maintenance and repair of all Diffusion and Etch equipment. Troubleshooting, repair, pump maintenance, logging of actions thru CCEMS. Daily PM’s, WJ injector changes, MFC calibrations, CVD susceptor changes, chamber cleans gas bottle changes. Training of junior technicians, writing maintenance procedures to be ISO 9000 compliant. Emergency response team leader for C-shift.
Senior Diffusion Equip. Engineer
SGS Thompson
Phoenix, AZ
01.1996 - 11.1999
- Responsible for A-Shift maintenance and repair of all Diffusion equipment. Troubleshooting equipment, pump maintenance, logging of actions thru Work Stream database, and Lotus. Furnace tube changes, WJ muffle etch and injector changes, HDP maintenance, Quartz replacement, chamber cleans, calibrations, PM’s. Training of technicians, machine modifications, and responsibility for particle improvement plan for all diffusion equipment. Emergency response team member. Promoted to Equipment Engineer shortly after working with company.
Senior Etch Equipment Technician
Microchip Corp
Chandler, AZ
01.1987 - 12.1996
- Directed operations of furnace banks for oxidation and poly processes. Advanced to leadership role in the equipment maintenance and process group. Oversaw maintenance, repair, and evaluation of wafer etch and inspection equipment. Led troubleshooting efforts for equipment down to the component level. Managed gas bottle changes and implemented equipment upgrades and modifications. Coordinated calibrations and preventive maintenance initiatives. Authored maintenance instructions and developed preventive maintenance schedules. Mentored junior technicians on equipment repair and preventive maintenance best practices. Completed in-house training on process flow and CMOS processing to enhance operational efficiency. Resolved critical process issues systematically. Served as a vital member of the emergency response team. Assumed leadership as shift command team leader. Pioneered initiatives as a founding member of the Applied Material Lam Particle Reduction Enhancement Team.
Education
AA degree - Technology-Electronics/Computer Engineering
Miller Institute/ITT TECHNICAL INSTITUTE
Phoenix, AZCompleted 2 Semester Course Credit - Mask layout design
MESA COMMUNITY COLLEGE
Mesa, AZSkills
- Layout optimization
- Shielding, common centroid, design with parasitics in mind
- Relationship building
- Hierarchy Design planning
- Cross-platform design with different sub-micron technology finfet
- Robust design principles
- Interpersonal and written communication
- macro design and consistency
Timeline
Principal Layout designer
Microchip Technology
12.2022 - 06.2026
Mask Design Engineer
Intel Corporation
03.2021 - 08.2022
Mask Layout Engineer Contractor
Qualcomm, Inc.
12.2014 - 04.2016
Analog IC Layout Designer Contractor
Cirrus Logic, Inc.
09.2013 - 08.2014
Hydole Power Electronics Hardware Engineer
Freescale Corp.
10.2010 - 08.2013
Mask Layout Engineer
Freescale Corp.
11.2007 - 02.2010
Mask Layout Engineer
Infineon/Qimonda RTP Design Center
05.2005 - 10.2007
Analog IC Layout Designer-Contractor
Intersil Corporation, Seattle Design Center
01.2004 - 02.2005
Layout Design-Engineer
Virage Logic Corporation, Seattle Design Center
09.2001 - 05.2003
Senior Diffusion/Etch Engineer
Microchip Corp
01.2000 - 08.2001
Senior Diffusion Equip. Engineer
SGS Thompson
01.1996 - 11.1999
Senior Etch Equipment Technician
Microchip Corp
01.1987 - 12.1996
AA degree - Technology-Electronics/Computer Engineering
Miller Institute/ITT TECHNICAL INSTITUTE
Completed 2 Semester Course Credit - Mask layout design
MESA COMMUNITY COLLEGE