Summary
Overview
Work History
Skills
Work Availability
Work Preference
Software
Timeline
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Scott Harrenstein

Scott Harrenstein

Fort Collins,CO

Summary

Accomplished Sr. Layout Designer at Intel, renowned for optimizing chip performance through advanced physical design and power grid techniques. Excelled in cross-functional collaboration, ensuring timely project delivery. Mentored junior engineers, enhancing team knowledge and productivity. Skilled in layout optimization and effective communication, significantly improved design robustness and reduced turnaround times.

Overview

34
34
years of professional experience

Work History

Sr. Layout Designer

Intel
10.1990 - 10.2024
  • Achieved optimal chip performance by implementing efficient physical design methodologies and tools.
  • Collaborated with cross-functional teams to ensure smooth project execution and timely delivery of designs.
  • Implemented innovative solutions to overcome challenges related to signal integrity, electro-migration, and IR drop.
  • Resolved complex physical design issues promptly, minimizing delays in project timelines while maintaining high standards of workmanship.
  • Delivered high-quality floorplans by working closely with front-end designers on constraints development and partitioning strategies.
  • Provided valuable feedback during design reviews, contributing to ongoing improvements in product quality and performance.
  • Mentored junior engineers in industry best practices, fostering a positive learning environment within the team.
  • Established effective communication channels between engineering teams globally, promoting collaboration on shared objectives and goals.
  • Identified and resolved critical issues in layout routing, significantly improving overall design robustness.
  • Enhanced design quality and reduced turnaround time through automation of various design tasks.

Skills

  • Layout optimization
  • Power Grid Design
  • Design Rule Checking
  • Floorplanning Expertise
  • Low Power Design
  • Interpersonal and written communication
  • Analog Circuit Design
  • Custom Layout Design
  • Physical Verification
  • Advanced VLSI Design
  • Routing Techniques
  • Standard Cell Library Development
  • EDA Tool Proficiency

Work Availability

monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Work Preference

Work Type

Full Time

Location Preference

On-SiteRemoteHybrid

Important To Me

Work-life balanceCareer advancementCompany Culture

Software

Xcel

Wrod

Power point

Timeline

Sr. Layout Designer

Intel
10.1990 - 10.2024

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Scott Harrenstein