R Kugen Raj Ramanathan
Portland,OR
Summary
Results-oriented Software Validation Engineer with comprehensive knowledge in software quality assurance, testing methodologies and validation strategies. Proven record of ensuring that software products meet strict regulatory standards before release. Emphasizes clear communication between development teams and stakeholders to facilitate error correction and product refinement processes. Demonstrates strong problem-solving abilities, technical expertise, and team leadership skills to drive projects to completion.
Overview
13
13
years of professional experience
Work History
System Software Validation Engineer
Intel Corporation
Hillsboro, Oregon
03.2017 - Current
- Spearheaded platform power-on for a new product, coordinating efforts with a global team of engineers. Key tasks included system bring-up with predefined validation setups, enabling product features across all SOC IP and platform domains, resolving critical functional and stability issues through debug forums, and aligning firmware and software into a unified stack.
- Focus primarily on validation in the domains of Power Management, Type-C Subsystem, and Design for Debug (DFD).
- Contributed to the silicon debug feature implementation on Intel products, and worked with external customer teams to integrate Intel DFD solutions, improving debugging, and accelerating issue resolution and time-to-market.
- Expert in Intel debug solutions, leading lab infrastructure modernization with a 90% cost reduction.
- Contributed to the complete Product Life Cycle (PLC) of a client product, from pre-silicon design stages to post-silicon validation. Conducted pre-silicon validation using simulation tools, hybrid simulation, and FPGA to confirm that functionality meets design specifications.
- Develop and maintain test automation frameworks to validate critical feature functionality, and prevent regressions in the integrated firmware and software stack.
- Perform silicon and platform debug to root-cause issues and enable robust design fixes using the on-chip debug features (Intel DCI, NPK, ISD NDA, MIPI JTAG) and test equipment (Logic Analyzers, Protocol Analyzers, Oscilloscopes).
- Proficient in HW, SW, and FW debugging to isolate, root cause, and analyze system failures.
- A developed understanding of computer architecture, CPU microarchitecture, and disaggregated system architecture.
- Confident in navigating the uncertainties of the initial stages, and driving progress toward clear and impactful results.
- Demonstrated collaboration, communication and leadership skills.
Low Power Analysis Intern
Intel Corporation
Santa Clara, California
09.2016 - 03.2017
- Performed platform bring up and power & performance analysis on devices ranging from micro server, handheld to IOT
- Conducted directed studies on competitive mobile SOC via measurements, benchmarking or projection and contribute solutions to drive power, performance and architectural change on next generation products
- Performed power modelling for micro server SOC in terms of core and uncore module using Docea Power Analytics tool
Graduate Student Research Worker
University of Texas at Dallas
Texas
07.2015 - 09.2016
- Responsible for developing circuit design and layout for biosensor related application
- Developed a novel circuit design for Pico-to-Nano ampere range current sense application from concept and proof of principles to specifications and implementation in 6 months
- Hands-on with both simulations and lab measurements to validate the simulation results
FPGA & Test Development Engineer
Intel Corporation
Kulim, Malaysia
01.2013 - 12.2014
- Led and coordinated a cross-functional team of 8 people to develop project schedules and supported mass manufacturing activity for 3 products concurrently
- Decreased the designing and verification time by developing FPGA codes to verify and evaluate tester modules for the burn-in and functional test of SOC
- Maximized the productivity by 25% with limited man power by getting involved in all three schematic design, layout and manufacturing support of HDI motherboard tester modules
- Well informed with technology path-finding, design material gathering, conducting design review, designing test/fixture, resolving design and implementation issues as needed through product life cycle
- Conducted fab spin project and make appropriate design changes, drive new BOM and initiate rework instructions to the factory
R&D Hardware, Design & Validation Engineer
Intel Corporation
Kulim, Malaysia
01.2012 - 12.2013
- Involved in developing Atom SOC Compute Modules in 8–10 layers HDI board with CPU and DIMM solder down
- Delivered the 7.1 audio test board and CPU enabling functional modules reference design for expanding atom CPU in in-vehicle infotainment 'IVI' market
- Performed high speed digital board design schematic entry, layout routing, layout optimization and post-manufacturing validation and debugging of PCB and SOC CPU to ensure the correct functionality and signal integrity analysis
- Added experience in analog and digital circuit design, schematic capture, and PCB layout
- Knowledge of electromagnetic and transmission line theory, high-speed circuit design, RF, electrical concepts, signal integrity and analysis tools
- Acquainted with the use of Cadence Allegro, Mentor Graphics PADs and Pspice
- Competent in analyzing timing, noise margin, crosstalk, signal loss and signal integrity of all clocks and critical data signaling (single-ended and differential signals) and develop noise and timing budgets
- Conduct technical design reviews with peers and stakeholders, to ensure the reference design co-align with respect to the design guide
Education
Master's degree - Electrical and Electronics Engineering
The University of Texas at Dallas
12.2016
Bachelor's degree - Electrical and Electronics Engineering
Northumbria University
12.2012
Diploma - Electrical and Indstrial Electronics Engineering
Universiti Malaysia Pahang
12.2010
Skills
- Regression testing & continuous integration
- System level debug accuracy and throughput
- Silicon debug features
- Functional validation strategy
- System bring-up or platform power-on
- Test like customers
Academic Experience
- Advanced VLSI Design
- Analog IC Design
- Computer Architecture
- Digital Signal Processing
- Microprocessor
- RFIC Design
- Trusted and Secure Integrated Circuits and Systems
- VLSI Design
Languages
- English, Native
- Malay, Native
- Tamil, Native
Timeline
System Software Validation Engineer
Intel Corporation
03.2017 - Current
Low Power Analysis Intern
Intel Corporation
09.2016 - 03.2017
Graduate Student Research Worker
University of Texas at Dallas
07.2015 - 09.2016
FPGA & Test Development Engineer
Intel Corporation
01.2013 - 12.2014
R&D Hardware, Design & Validation Engineer
Intel Corporation
01.2012 - 12.2013
Master's degree - Electrical and Electronics Engineering
The University of Texas at Dallas
Bachelor's degree - Electrical and Electronics Engineering
Northumbria University
Diploma - Electrical and Indstrial Electronics Engineering
Universiti Malaysia Pahang
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