Samir Pandya
Folsom,USA
Summary
Accomplished GPU Logic Design Engineer with extensive experience at Intel Corporation, specializing in RTL design and team mentorship. Led the development of innovative graphics system interactions and validation processes, resulting in substantial cost savings and pending patents. Demonstrates strong collaborative skills and a commitment to continuous learning while excelling in diverse roles.
Overview
15
15
years of professional experience
Work History
GPU Logic Design Engineer
Intel Corporation
Folsom, USA
06.2017 - Current
- Directed core functions of the Shader Core's Thread Control unit across multiple GPU types (Discrete, HPC/AI, Client) containing Deep Learning and AI applications.
- Managed and coordinated tasks for both the Message Execution unit and Vector Branching Unit.
- Facilitated more efficient interaction within graphics system by implementing advanced message handling.
- Handled various branching operations to maintain efficient execution of conditional branches, calls and jumps.
- Worked closely with Driver, Hardware, Software architecture & model teams to lead micro-architecture development.
- Maintained functional integrity across pre-silicon and emulation phases.
- Collaborated with physical design, power, and performance teams to meet project goals.
- Supported team growth through mentorship of junior engineers and interns.
- Patents: Few pending approvals
Product Development Engineer
Intel Corporation
Folsom, USA
06.2012 - 06.2017
- Conducted validation processes for GFX Silicon across multiple hardware configurations.
- Performed RTL simulation and conducted detailed debugging for pre-silicon validation.
- Ensured silicon functionality on wafers during the Sort phase and on packaged units at Class through post-silicon validation.
- Developed and implemented a robust RTC leakage test, recovering up to 4% of U/D issues and generating $15M in savings.
ASIC Verification Engineer (Contract)
Qualcomm Inc
11.2011 - 06.2012
- Under the guidance of senior designers validated the Snapdragon CPU processors various level of sleep sequences of different caches
- Validate all the architecture resources states depending upon the sleep state by test codes, which were written on Assembly language
- Synopsys VCS, Modelsim and Verdi tools were used for RTL simulation and debug
Design Engineer (Intern)
Biomedical Resource Group
CA, USA
05.2010 - 08.2010
- Engaged in logic design and low-level programming (Assembly & C) for microcontroller
- Worked with oscilloscope, spectrum analyzer for data acquisition with the help of LabVIEW tool
Education
M.S - Electrical Engineering
California State University, Northridge
NorthridgeB.E - Electronics & Communication Engineering
Gujarat University
IndiaSkills
- RTL design
- Verification
- Simulation
- Synthesis
- Timing analysis
- SpyGlass
- LIRA
- Verilog
- SystemVerilog
- Assembly
- Design tools
- Graphics Architecture Expertise
- Consistent Professional Integrity
- Positive attitude
- Proficient in Collaborative Interaction
- Committed to Continuous Learning
- Versatile Role Engagement
Timeline
GPU Logic Design Engineer
Intel Corporation
06.2017 - Current
Product Development Engineer
Intel Corporation
06.2012 - 06.2017
ASIC Verification Engineer (Contract)
Qualcomm Inc
11.2011 - 06.2012
Design Engineer (Intern)
Biomedical Resource Group
05.2010 - 08.2010
M.S - Electrical Engineering
California State University, Northridge
B.E - Electronics & Communication Engineering
Gujarat University
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