SANJANA
San jose,CA
Summary
Experienced Mask Layout Design Engineer with 6 years of industry experience in Memory Layout and SOC Design. Specialized in designing high-density multiport memory arrays and advanced memory architectures. Strong expertise in Intel leading designs across multiple process nodes (7nm, 5nm, 10nm) with a focus on performance,reusability, high density, and manufacturability.
Overview
6
6
years of professional experience
Work History
Mask Design Engineer
Intel Inc.
02.2023 - Current
- Designed 7nm high-density multiport memory arrays for SOC designs.
- Collaborated with cross-functional teams to ensure seamless integration at SOC level.
- Improved product quality by conducting detailed design reviews and implementing necessary changes.
- Managed multiple projects simultaneously while adhering to strict deadlines and maintaining a high level of attention to detail.
- Addressed design challenges and evaluated alternative design models to meet project requirements.
- Optimized existing designs, reducing production costs and enhancing overall performance.
Memory Layout Engineer
Intel Inc.
08.2020 - 01.2023
- Designed 10nm/7nm/5nm ROM and RF memory architectures
- Implemented ECOs and validated layouts using LVS/DRC tools
- Achieved a 39% reduction in IR values through EM and IR validation fixes
SOC Design Engineer
Intel Inc.
07.2019 - 07.2020
- Worked on Analog GPIO modelling.
- Owned the QA and Release methodology for customers.
Technical Intern
Intel Inc.
07.2018 - 06.2019
- Automated quality checks on GPIO packages using PERL scripting, significantly reducing time-to-release
- Gained hands-on experience with the XFIRE tool and PERL scripting for layout automation.
Education
Master of Technology - VLSI Design
Vellore Institute of Technology
07.2019
Bachelor of Engineering - Electronics and Communication
Sir M Visvesvaraya Institute of Technology
06.2017
Skills
- Memory Layout Design
- ECO Implementations
- LVS/DRC/Density and DFM validations
- EM/IR Fixes
- Scripting : PERL/TCL
- GPIO Modeling : Liberty and IBIS model generation
- RTL: Verilog HDL
TOOLS
- Cadence Virtuoso
- Genesys Layout Editor
- Synopsys Custom compiler
- Synopsys VCS
- Silicon Smart
Timeline
Mask Design Engineer
Intel Inc.
02.2023 - Current
Memory Layout Engineer
Intel Inc.
08.2020 - 01.2023
SOC Design Engineer
Intel Inc.
07.2019 - 07.2020
Technical Intern
Intel Inc.
07.2018 - 06.2019
Master of Technology - VLSI Design
Vellore Institute of Technology
Bachelor of Engineering - Electronics and Communication
Sir M Visvesvaraya Institute of Technology
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