Sean(Shuhui) Lu
Folsom,CA
Summary
22+ years working experience in the semiconductor industry; deep knowledge in high performance computing(HPC) systems; proven record of various products delivery and revenue creation in HPC segment.
Overview
25
25
years of professional experience
Work History
Senior Business Development Manager
TSMC Advance Technology Business Development
01.2021 - Current
- TSMC leading technology roadmap and business development covering TSMC N7/N6/N5/N3 process node
- Top tier HPC customer engagement for sever, client, mobile segment
- Account growth, penetration and market expansion.
Senior Engineering Manager
Synopsys Inc
05.2019 - 01.2021
- Drive StarRC & QCAP feature development to meet customer design requirements covering digital, analog, memory, CPU and 3DIC chiplet
- Interact with top tier semiconductor companies worldwide such as Intel, Apple, Nvidia, TSMC etc to provide debug and design consultancy
- Collaborate with multiple internal R&D teams to improve design technology in the area of high-performance computation, advanced field solver and latest AI application
Engineering Manager
Intel Corp Programmable Solution Group
04.2018 - 05.2019
- High Performance Computing and FPGA IP design
- Interact with customers, marketing, and application engineer to develop MRD/PRDs for top tier customers such as Ericson, Huawei, Cisco etc.
- Provided technical leadership for company to effectively steer strategic plans and future projects.
Engineering Manager
Intel Corp. CPU Core
06.2012 - 03.2018
- High performance CPU Core Cache Memory Design and Full Chip DFX committee Chair
- Manage and design mid-level cache functional unit for Intel 10nm CPU products
- Lead team to perform RTL to physical implementation including synthesis, schematic capture, simulation / margin verification across PVT, functional verification and timing closure
- Drive register file circuits optimization to fix critical uArch path to improve CPU Instruction Per
- Cycle (IPC) performance
- Develop and implement full chip DFX methodology to push CPU scan coverage above 80% along with other critical testing features such clock edge manipulation
- Circuit marginality validation (CMV)to correlate mismatch between system and high-volume manufacturing testers and provide performance guard band for various Intel CPU products
- Speed path root cause on high performance Intel CPU platforms that covers cache, graphic, storage and various IOs
- CPU/SOC system readiness and product power-on release for Intel client and server family.
SOC Chipset Memory Design Lead
Intel Corp
01.2010 - 06.2012
- High performance embedded memory design
- Lead team to design and implement custom Register File and SRAM circuits for Intel chipset products to serve 14-12nm CPUs
- Establish micro-architect specification (MAS) for chipset memory design
- Enhance and optimize memory to meet high speed and lower power requirements
- Research and perform technical readiness for next generation memory design based on new manufacturing process
Senior Component Design Engineer
Intel Corp
07.2005 - 12.2009
- Out-of-order (OOO) design for Intel mobile processors
- Owned and designed RS station for OOO cluster
- High speed and low power RF memory design
- Pre and Post Si Speed path identification and root cause
Networking Processor Division, Component Design Engineer
Intel Massachusetts
09.2000 - 07.2005
- 1.4 G High speed clock generation and distribution design for Intel
- IXP28xx networking processor
- Programmable high-speed clock driver circuit design
- Pre-layout/Post layout wire modeling for 1.4G recombination clock tree distribution
- Clock unit logic & circuit implementation
- Circuit performance analysis and verification
Process Integration Engineer
Chartered Semiconductor Manufacturing Ltd
03.1996 - 12.1998
- Process development and integration on 0.35 & 0.5um Logic, 0.35 & 0.45um SRAM, 0.45&0.6um ROM, flash memory and uLCD process
- Yield improvement and failure analysis on memory devices (SRAM/ROM).
Education
Master of Business Administration -
University of California
12.2010
Master of Science - Electrical Engineering, design
Pennsylvania State University, University
5.2000
Bachelor of Science - Electrical Engineering
Fudan University
7.1995
Skills
- Account Management
- Market and Competitive Analysis
- Team Leadership
- Business Management and Development
- Strategic Business Planning
- Computer hardware and VLSI design
- RegisterFile and Cache memory design
- Pre and post silicon validation and debug
- Python/C programming
- Semiconductor Manufacturing
Timeline
Senior Business Development Manager
TSMC Advance Technology Business Development
01.2021 - Current
Senior Engineering Manager
Synopsys Inc
05.2019 - 01.2021
Engineering Manager
Intel Corp Programmable Solution Group
04.2018 - 05.2019
Engineering Manager
Intel Corp. CPU Core
06.2012 - 03.2018
SOC Chipset Memory Design Lead
Intel Corp
01.2010 - 06.2012
Senior Component Design Engineer
Intel Corp
07.2005 - 12.2009
Networking Processor Division, Component Design Engineer
Intel Massachusetts
09.2000 - 07.2005
Process Integration Engineer
Chartered Semiconductor Manufacturing Ltd
03.1996 - 12.1998
Master of Business Administration -
University of California
Master of Science - Electrical Engineering, design
Pennsylvania State University, University
Bachelor of Science - Electrical Engineering
Fudan University