Sejal Gami
Endicott,NY
Summary
Experienced professional with 6 years in ASIC/FPGA verification domain. Proficient in developing reusable UVCs using SV and UVM methodology. Skilled in verifying DSP modules and adhering to DO-254 process for VCD and VPRD development. Actively contributed to SOI-3 Audit for VCD/test plan. Expertise in test case writing, debugging, and Test plan Development. Proficient in developing functional coverage plans and achieving full functional coverage. Experienced in third-party VIP configuration, integration, and environment development for different protocols. Strong background in RTL integration with VIP and test bench creation. Knowledgeable in IP/Subsystem level Verification. Skilled in Shell scripting and Perl & Python Scripting with OOPs. Hands-on experience with Questasim and Synopsys VCS. Strong debugging and communication skills.
Overview
6
6
years of professional experience
2
2
Certifications
Work History
Sr. ASIC Engineer
Alpha Numero Technology Solutions Inc
03.2023 - Current
- Worked with Design and Requirement Teams onsite to resolve failures, review verification test plan, coverage analysis and full-chip simulation for complex designs with 98% accuracy.
- Verified designs utilizing self-checking techniques with executing 100+ directed and constrained random tests to achieve 95% coverage while tracking functional and code coverage.
- Created complete design requirements, verification plan and user guides.
- Leading team and handling onsite-offshore communications.
Senior Verification Engineer
ANTS Global Systems Pvt Ltd
07.2022 - 02.2023
- Developed/Updated 300 test plans based on new requirements with no functional review comments from clients. Received "Excellent Execution" award from organization.
- Collaborated closely with clients to gather system-level requirements, resulting in definition of effective FPGA level test plan.
- Efficiently updated existing verification environment for new requirements without extra ramp-up time.
- Developed functional coverage and implemented analog data dumping against time series for ADC interfaces.
- Developed and debugged fixed-point math verification environment for various filters, limiters, and 6 low-level math components.
- Demonstrated thorough understanding of system-level data flow and usage to stimulate critical DSP blocks at PLD and block level, and gathered response data for checking data.
Senior Engineer
Capgemini Engineering
09.2011 - 07.2022
- Creating testcases for PCIe Switch IP Architecture Requirements.
- Experience in developing verification components like Driver, Monitor and Scoreboards.
- Debugging regression failures in VCS Verdi Waveform tool.
- Integrated verification IP of user defined serial data transfer protocol. Updated verification IP to incorporate erroneous cases.
- Creating wrapper blocks for PCIe Gen 3 and 4 Soft IP for intended design.
- Involved in generating erroneous scenarios for Advanced Error Reporting.
- Involved in verifying TLP packets converting to other interfaces like bypass control, AXI-Lite, Custom Memory Mapped interface, etc.
- Mentored and coached entry-level and junior engineers to improve talent and boost skill levels
Senior Verification Engineer
ANTS Global Systems Pvt Ltd
08.2017 - 09.2021
- Hands on experience on creating verification artifacts compliant to DO-254 DAL Level-A.
- Experience in developing verification components like Driver, Monitor, Predictors, Scoreboards.
- Excellent in defining functional coverage and assertion.
- Updated existing verification environment to make it debug friendly which helped debugging failures with single time generated results.
- Integrated verification IP of user defined serial data transfer protocol. Updated verification IP to incorporate erroneous cases.
- Developed configurable verification components in SV for fixed-point math operations like multiplier, adder, subtracter, IIR-Filter, Updown Counter, Lookup tables, etc.
- Updated python script helped to create classes defining characteristic/functionality of each field.
- Communicate independently with client regarding design failures.
- Experience on executing project with Agile Methodology.
Education
Bachelor of Engineering - Electronics And Communications
Gujarat Technological University
Surat, India06.2015
Skills
- Operating Systems: Windows, Linux
- Programming Languages: C, C, MATLAB
- HDL Language: VERILOG, VHDL
- HVL Language: System Verilog
- HVL Methodologies: Universal Verification Methodology (UVM)
- Scripting Languages: Python, Perl, Make, ITF, Avatar
- Version Control Tools: SVN, Helix P4
- EDA Tools: Synopsys VCS, Mentor Graphics QuestaSim
- DO-254 Process Applicable Tools: DOORs
- Software Packages: Synopsys VCS, QuestSim, Xilinx, Quartus II, PSPICE, MATLAB, LabView
- Hardware Tools: FPGAs of Xilinx and Altera, ARM Cortex, Arduino, Raspberry Pi
Certification
- SystemVerilog Certification by Siemens on April 2020.
- UVM Certification by Siemens on May 2020.
- Linux Training by IIT, Bombay on March 2014.
Timeline
Sr. ASIC Engineer
Alpha Numero Technology Solutions Inc
03.2023 - Current
Senior Verification Engineer
ANTS Global Systems Pvt Ltd
07.2022 - 02.2023
Senior Verification Engineer
ANTS Global Systems Pvt Ltd
08.2017 - 09.2021
Senior Engineer
Capgemini Engineering
09.2011 - 07.2022
Bachelor of Engineering - Electronics And Communications
Gujarat Technological University
- SystemVerilog Certification by Siemens on April 2020.
- UVM Certification by Siemens on May 2020.
- Linux Training by IIT, Bombay on March 2014.
Similar Profiles
SUSHMITA GANGULYSUSHMITA GANGULY
Preschool Administrator at Alpha Numero International PreschoolPreschool Administrator at Alpha Numero International Preschool
Keith WitherspoonKeith Witherspoon
Auxiliary Worker at Alpha Productions TechnologyAuxiliary Worker at Alpha Productions Technology
VIJAY BASKAR MANOHARANVIJAY BASKAR MANOHARAN
Consultant at ALPHA ORI TECHNOLOGYConsultant at ALPHA ORI TECHNOLOGY