SHALINI S K
FPGA Design & Verification
BENGALURU,KARNATAKA
Summary
Ø Hands on experience in writing RTL Coding in Verilog and VHDL, FSM based Design, Simulation and Synthesis.
Ø Expertise in Testbench development and behavioral models.
Ø Generating functional and code coverage for RTL verification.
Ø Good knowledge of debugging issues of Design.
Ø Good understanding of FPGA design flow.
Ø Worked on QuestaSim, and Xilinx Vivado tools to debug and simulate.
Ø Hands on experience in writing Test cases in Verilog.
Ø Good Knowledge in writing Bus Functional Model (BFM) to verify each module by writing test cases.
Overview
4
4
years of professional experience
Work History
FPGA Design Engineer
Capgemini Technology Services
Chennai, Tamil Nadu
02.2018 - Current
· Test bench environment development · Test cases creation to test for various scenarios · RTL issues Debugging and reporting for test failures · Makefile Scripts and shell scripts development for test regression · Functional Coverage module development and performed on RTL Code Coverage
4+ Years of experience in front end RTL design and Verification.
Hands on experience in writing RTL Coding in Verilog and VHDL, FSM based Design, Simulation and Synthesis.
Expertise in Creating Testbench Environment and Behavioral models
Very good exposure in Debugging RTL
Efficient in converting Specification to RTL, including Verilog HDL and VHDL
Project Details
MUX FPGA
Roles and Responsibilities.
· Developed design Document
· Worked on RTL Implemention for HOT-Standby Switch and Dual PHY
· The designed modules are verified through simulation using ModelSim and synthesized using Altera Quartus prime standard edition
· Integrated Ethernet Bridge, Protection Control, SGMII Mux Control and One pps modules.
· Developed BFM’s, testcases and verified in questasim for Integrated modules.
· Developed unit level tesbench for HSBY switch and Dual PHY. Created testcases to verify the functionality of Design.
· Developed BFM’s for SPI, I2C, GPI, OMI and UART
· Implemented scoreboard, checkers
Reticle Handler Local Input / Output and Safety Board
Roles and Responsibilities
· RTL Integration of BROM and PLL Modules
Education
Guide Line Convent
ShravanabelagolaSkills
RTL Design and verification
Timeline
FPGA Design Engineer
Capgemini Technology Services
02.2018 - Current
Guide Line Convent