Shrividhya Srinivasan

Dynamic professional with a strong background in database management and programming, honed at Cognizant Technology Solutions. Proficient in SQL and Python, I excel in problem-solving and collaboration, driving successful software enhancements and automated solutions. Recognized for outstanding performance, I effectively support complex systems and foster positive relationships with stakeholders.

• CMOS
• FPGA
• Simulation & Synthesis
• Timing Optimization
• Code Coverage
• Cache Memory Concepts
• MESI Protocol
• ASIC Design Flow
• Digital logic design
• SRAM
• DRAM
• Oscilloscope
• PCI

• Design of Parallel-to-Serial Transmit Interface (PSI), Designed a parallel-to-serial transmit interface using Verilog HDL capable of receiving data packets from DMA, convert to serial data with delimiters and transmit as serial output. Design was tested by 16KB of random sequence and performed a synthesis and simulation using Synopsys tool.
• Design and Layout of an Overlapping Sequence Detector, Designed using JK Flipflops based on TSMC 180nm process and satisfied DRC & LVS checks. Achieved a 30% reduction in layout size and minimized power consumption.
• Design of a Memory, Designed a memory circuit consisting of D-flip flops to store the data inputs and interconnecting wires and logic gates. A Verilog testbench compares the output of the designed circuit and expected output generated by Perl program.
• Design of 8-bit ALU, Designed an 8-bit ALU which performs arithmetic and logical operations. A Verilog testbench compares the output of the designed circuit and expected output generated by Perl program.

Golden Clove Award for Best Performer – Cognizant Technology Solutions August 2013

• In recognition of outstanding efforts in completing my deliverables well before the deadline.

Customer Champion Award – Cognizant Technology Solutions September 2015 & 2016

• In recognition towards my contribution and efforts to the Cognizant Infrastructure Services.