Sravan Kumar Donakonda
ROUND ROCK,TX
Summary
Adept STA CAD Engineer with a proven track record at Ericsson, where I spearheaded the development of a Primetime based STA methodology and design team support. Excelled in Python scripting and mentoring, demonstrating exceptional problem-solving skills and the ability to thrive under pressure.
Overview
9
9
years of professional experience
Work History
STA CAD Engineer
Ericsson
06.2022 - Current
- Developed Primetime based STA methodology from scratch using Synopsys RM flow has the start point. Implemented the flow such that it supports block level and SOC level STA.
- Enablement of timing checks like setup, hold, recovery, removal, timing drc violation checks using PBA/GBA types depending on quality of the project across multiple scenarios and test modes using Primetime DMSA.
- Developed a utility to identify dominant scenarios in a STA run. This uses an algorithm that considers violating endpoints counts and their negative slack to determine the dominant corner. This helped designers to focus on smaller set of scenarios when running Primeclosure ECO cycles minimizing core usage and overall run time.
- Implemented IO virtual clock latency calculation procedure that sets latency on IO paths for better timing closure in SOC environment.
- Developed budget adjust mechanism on IO timing paths to lock in the budget available for the blocks/partitions. Those timing paths would have slack closer to 0 after the adjustment.
- Accomplished ETM generation flow that produces extracted timing model at block level so the liberty file can be consumed at SOC top level STA. Worked on padding the generated ETM so SOC would see 0 slack on the block's IO paths.
- Successfully enhanced the flow to support library scaling. This allowed users to run their timing and power analysis at different voltages and temperatures.
- Worked on implementing a feedback loop between EMIR and STA flows. Flow will run voltage drop per instance based STA using the IR drop values from EMIR flow and disabling user defined IR derate.
- Developed and currently maintain library management API that delivers necessary .libs/dbs for all blocks based on PVT and extraction requirements. This API supports std cells, memory macros and different third party IPs like SerDes, PLL, GPIOs, pvt sensors etc.,
- Implemented parquet db based library methodology to lock in the scenario list and release versions.
- Worked on numerous python based post process reporting scripts that generate reports in the form of CSVs, histograms, tables for designers and leads to better understanding of QOR.
- I was part of dashboarding team that develops and publishes results dashboard for users to get quick looks of their block metrics.
- Mentored and trained interns on team for successful onboarding and produce meaning results. Delegated tasks per the requirement.
CAD Engineer - Crosscheck QA Tool
Intel
03.2016 - 06.2022
- Developed and maintained QA tool and methodology for IP level memory compiler design team. I worked on custom developed internal tool written using PERL, Shell, Ruby and HTML and also industry standard Crossfire (now Crosscheck) tool from Siemens. I have written over 100+ checks using Python APIs in Crosscheck and enabled design teams to run QA on views like RTL, LEF, GDS, liberty and many others.
- Implemented platform spec vs memory instance checking using YAML config. Used python Jinga2 library to render YAML spec and extract expect data.
- Developed checks extensively for datasheet vs liberty files. Compared timing. leakage power, capacitance, area and pin consistency data between those view.
Education
Master of Science - Electrical Engineering
The University of Texas At Dallas
Richardson, TX12-2015
Skills
- Python scripting
- Problem solving
- Git version control
- Jenkins
- Debugging
- Work really well under pressure
- Mentoring
Timeline
STA CAD Engineer
Ericsson
06.2022 - Current
CAD Engineer - Crosscheck QA Tool
Intel
03.2016 - 06.2022
Master of Science - Electrical Engineering
The University of Texas At Dallas
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