Summary
Overview
Work History
Education
Skills
Timeline
Hi, I’m

Sriharsha Vinjamury

Staff Engineer/Manager
Austin,TX

Summary

10.5 years Post Silicon experience with Specialization on ATE bring-up and Characterization of Mobile and Server Chips. Analytical, organized Lab Manager with [Number] years in leading team to develop [Type] products in laboratory setting. Initiated and analyzed new product development and improved current product line. Streamlined lab processes and worked with other departments to prioritize tasks with strongest effect on revenue.

Overview

11
years of professional experience

Work History

Lab Manager

Job overview

  • Drove Critical IP bring up (NPI) and HVM activities for blocks like CPUs, HSIO ()
  • Drove Pre-silicon and post Silicon activities
  • Cost Quality and Tim-to-Market, Lab bring-up
  • Tester Bring-up
  • Process improvement
  • QUAL
  • Board Design recommendations and Reviews
  • Test Plans
  • Partial Good
  • Flowcharts
  • SM8 and IG-XL
  • HW
  • New Hire
  • Cross-Platform correlations.

Qualcomm technologies inc
Austin, TX

Test Engineer
05.2015 - Current

Job overview

  • Bring-up of first time IP 8 lane Gen-4 PCIe Silicon Validation and Debug for Memory BIST, VDIP/VDR, PLL testing on 14 and 10nm Server Products
  • Issue debug, PVT data, Data analysis, review with team followed by Production Release
  • Wrote various scripts for faster execution of manual tasks
  • Examples include: Flow variable checks, Pattern breakdown from differential to single ended pins, Pattern Tag check and report tools etc
  • Worked on Various Characterization Activities like PLL: Lval sweep, Fmin/Fmax, Lock Detect; VDIP/VDR: Write/read Margin sweeps, VMIN searches etc
  • CRES for GPIO and HSIO Pins on wafers to find data trends to avoid socket/Probecard burns
  • In process of developing an algorithm that runs the CRES test once every few dies to get a trend of socket health
  • Trend are then compared to its predecessor to recommend socket/PC cleaning
  • Test time reduction techniques like loop count reduction through coding, test program updates, pattern ranking
  • Testing at faster speeds implemented successfully.

Freescale, NXP

DSP Test/Product Engineer
08.2012 - 05.2015

Job overview

  • Worked on developing Test programs for production flow at Final test level
  • Responsible for program releases for Qualification, Final test, yield management and Test time reduction
  • Implemented various test time reduction techniques
  • A few examples include: Pattern Compressions, Multiport Pattern Bursts, Writing faster Test codes in VB
  • Worked on testing IP blocks such as EIM and UART for Functionality, Robustness across process, voltage and temperature as well as characterizing these blocks for timing specifications like Input setup, Input Hold, Output Delay, data skew etc
  • Responsible for generating Cp, Cpk, distribution charts using JMP
  • Worked on writing software to perform faster searching during Characterization
  • Converted all Linear search Algos to Binary for the Project.

Education

Texas Tech University (TTU)

M.S from Electrical Engineering

University Overview

GPA: 3.68

Jawaharlal Nehru Technological University (JNTU)

B.S from Electrical Engineering

University Overview

GPA: 3.47

Skills

93K, IG-XL

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Timeline

Test Engineer

Qualcomm technologies inc
05.2015 - Current

DSP Test/Product Engineer

Freescale, NXP
08.2012 - 05.2015

Lab Manager

Texas Tech University (TTU)

M.S from Electrical Engineering
08.2012

Jawaharlal Nehru Technological University (JNTU)

B.S from Electrical Engineering
05.2010

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Sriharsha VinjamuryStaff Engineer/Manager