Summary
Overview
Work History
Education
Skills
Timeline
Generic

Stephen Hughes

Rio Rancho

Summary

Accomplished Process Engineering Manager at Intel, leading advancements in ALD technology and defect reduction. Expert in mentoring junior engineers and facilitating 8D/FMEA. Spearheaded successful technology transfers and quality improvements, enhancing factory operations. Recognized for sustaining excellence and driving root cause analysis, achieving a 20% reduction in defects across diverse toolsets.

Overview

29
29
years of professional experience

Work History

Process Engineering Manager

Intel
05.2024 - Current

Process Engineering Manager in F9 Die Sort Module

Management of Junior process Engineering team

Coach for several internal Taskforce

8D presentation to Factory Management and Intel Product Group for MRB Related issue

Strategic planning of Equipment relative to Factory commits

Mentor to various other Groups including Integration and MPE

Coach to Virtual Factory OCAP improvement Teams

Senior Process Engineering Manager

Analog Devices
06.2021 - 04.2024

Process Manager of several Modules including Thin Films, Metal Deposition and Rapid Thermal Anneal

leading factory cost program promoting improvement and efficiency

Accountable for yield optimization initiatives employing DOE

Process Enhancment

Process Engineering Manager

Intel
03.2011 - 06.2021

process group leader for thin films chemical vapor deposition, high-density plasma, and chemical deposition technologies

advancement of ALD process and effective technology ramp-up to virtual factory sites

thin films quality liaison at factory quality meeting

leadership training and mentoring for process engineering teams

Head of mid-section IMT working group committed to reducing defects across diverse toolsets

multiple presentations at factory 3D meeting for senior management - issue resolution

Process Engineer

Intel
09.2007 - 03.2010

Process Engineer working in Thin Films responsible for developing new Technologies and successful transfer to virtual factory sites

Process Engineer responsible for Tool Availability, Matching, SPC Control and FMEA

Quality and IMT representative for Thin Films

Process Engineer

Intel
05.2002 - 09.2007

process engineer focused on 1262 and 1264 technologies within CDO module

executed seed assignment to d1d

overseeing process startup technology transfer and accelerated ramp for manufacturing

Manufacturing Engineer

NEC Semiconductors
06.1997 - 05.2002
  • Utilized project management metrics and tools for oversight of engineering and manufacturing projects and program services.
  • Advocated design for manufacturability principles.
  • Formulated and managed sub-contracting and outsourcing strategies for machining and processes to resolve in-house production challenges.

Education

Bachelor of Science - Electrical And Electronic Engineering

Strathclyde University
06-1997

Skills

  • Safety and quality role model
  • Development and Mentoring of Junior Engineers
  • 8D/FMEA facilitator
  • Sustaining excellence and root cause Analysis

Timeline

Process Engineering Manager

Intel
05.2024 - Current

Senior Process Engineering Manager

Analog Devices
06.2021 - 04.2024

Process Engineering Manager

Intel
03.2011 - 06.2021

Process Engineer

Intel
09.2007 - 03.2010

Process Engineer

Intel
05.2002 - 09.2007

Manufacturing Engineer

NEC Semiconductors
06.1997 - 05.2002

Bachelor of Science - Electrical And Electronic Engineering

Strathclyde University
Stephen Hughes