Subramanyam Yadavilli
Chicago,Illinois
Summary
Graduate student in Electrical and Computer Engineering with hands-on experience in VLSI circuit design, RTL development, and low-power architecture using FinFET technology. Skilled in Verilog, System Verilog, and HSPICE, with practical knowledge of Cadence and Synopsys tools for physical design, simulation, and verification. Strong project background in memory design, FPGA prototyping, and ASIC implementation.
Overview
1
1
year of professional experience
Work History
FinFET-Based Low-Power Logic and SRAM Design
Illinois Institute of Technology
11.2024 - 12.2024
- Designed 8-input Dual-Vt Domino Logic gate using 7nm FinFETs, reducing static power consumption by over 50% compared to standard low-Vt designs via sleep-switch integration.
- Developed and validated both 6T and 8T SRAM cells, with 8T design achieving 100% balanced leakage under all bit line/data conditions, mitigating side-channel vulnerabilities.
- Performed HSPICE simulations to analyze delay, power, and leakage; demonstrated ~35% reduction in subthreshold leakage using RVT/SRAM transistor optimization.
FPGA-based Hardware Accelerator for VGG11
Illinois Institute of Technology
10.2024 - 11.2024
- Designed and implemented hardware accelerator for VGG-11 on FPGA, reducing computation cycles by 67%.
- Developed synthesizable implementation on PYNQ-Z2, cutting resource use by up to 40% using optimizations.
- Explored design space by adjusting PE array sizes and tile configurations, improving memory access efficiency by 30%.
Advanced ALU Integration in 32-bit Pipelined CPU
Illinois Institute of Technology
10.2023 - 11.2023
- Implemented a 32-bit pipelined CPU in Verilog with a modular ALU supporting arithmetic, logic, and comparator operations; achieved multi-cycle instruction execution with proper synchronization.
- Compared four adder architectures (CRA, CLA, CSA) using synthesis and post-layout simulations, with up to 45% improvement in delay and area trade-offs analyzed across designs.
- Integrated a tree-structured 32-bit comparator into the ALU and verified design correctness via Synopsys Formality, ensuring robust performance and scalability.
Education
Master of Science - Electrical and Computer Engineering
Illinois Institute Of Technology
Chicago, Illinois05.2025
Bachelor of Technology - Electronics and Communication Engineering
KL University
Guntur, AP05.2023
Skills
- Skills: Physical design, Static Timing Analysis, low power design, Verilog, System Verilog, C programming, Java
- Tools: Xilinx-Vivado, Cadence Virtuoso, Formality, ICC2, Cadence Xcelium, H-spice
Publications
Design of Low Power Dual Gate MOSFET with Oxide Stacking and Comparison of Discrete Spacer Engineering
- Designed a dual-gate MOSFET with stacked high-k/low-k dielectrics (TiO₂/SiO₂) and discrete spacers tominimize leakage and enhance electrostatic control.
- Achieved ~85% improvement in drain current and a high ION/IOFF ratio (>5700), with improved threshold voltage and transconductance performance.
- Conducted device-level simulations using Silvaco TCAD (Atlas) with advanced models (CONMOB, FLMOB, AUGER), demonstrating viability for sub-30nm low-power CMOS technologies.
Timeline
FinFET-Based Low-Power Logic and SRAM Design
Illinois Institute of Technology
11.2024 - 12.2024
FPGA-based Hardware Accelerator for VGG11
Illinois Institute of Technology
10.2024 - 11.2024
Advanced ALU Integration in 32-bit Pipelined CPU
Illinois Institute of Technology
10.2023 - 11.2023
Bachelor of Technology - Electronics and Communication Engineering
KL University
Master of Science - Electrical and Computer Engineering
Illinois Institute Of Technology
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