Thanh Phat Phan
Fremont,CA
Summary
With over 10 years of experience spanning from RTL design to GDSII, I am proficient in operating EDA software from Cadence, Synopsys, and Mentor. Additionally, I have the ability to analyze and develop tools and scripts using Perl, TCL, Python and Shell to support design processes.
Overview
10
10
years of professional experience
2014
2014
years of post-secondary education
Work History
Senior Physical Design Technical Lead
Quest Global Inc
01.2022 - Current
- Contractor for Apple Inc
- Successfully taped out 3 projects (Barbet, Pandia, Pandia_Prime)
- Managed complex designs with 27 power domains, 400+ macros and over 3 million instances
- Managed the PPA (power, performance, area) optimization to meet stringent design target
- Designed scripts to improve the PD flows to increase team productivity and efficiency
- Solved all the critical issues related to timing, SDC, clock skew, xtalk, DRVs, PV, IREM, and more
- Led the physical implementation of SoCs from gate netlist to GDSII for advanced node technologies (3nm, 5nm)
- Mentored team member and provided technical guidance
- Led tapeout activities and ensure timely project delivery
Staff Physical Design Engineer
Synapse Design Automation Inc
02.2019 - 12.2021
- Contractor for Socionext Inc (Jul 2021 - Dec 2021): Successfully taped out a 12nm project (M2VES4)
- Contractor for Socionext Inc (Feb 2019 - Jun 2021): Successfully taped out a turnkey project (M2V) from test chip to production
- Key Responsibilities: Worked on ICC2 flow and handled critical designs with 6M instances, 700 macros, and 3 power domains
- Built complete flows for PNR, STA, DRC, LVS, ERC, ANT, LEC, and IREM
- Debugged constraints, fixed timing, and handled high-speed designs (4GHz, 2GHz, 1GHz)
- Led PV flow development for block and top-level designs
- Collaborated with STA, DFT, and PA teams to solve timing, IR drop, powerEM, and signalEM issues
Physical Design Lead
Synapse Design Automation Inc
03.2018 - 01.2019
- Contractor for Cadence Design Systems
- Successfully taped out 3 projects DDR4 32 bits and 1 project DDR4 64 bits
- Worked on PHY TOP design from floorplan to GDS used tool Innovus
- Taked care bump plan, RDL route, IO sequence, ESD insertion, power plan, PLL placement
- Used Tempus for timing closure
- Taked care DRC, LVS, ERC, ANT, signal EM, min pulse width (MPW), power analysis…etc
- Worked on high speed design (3200Mhz) and very tight data skew requirement (30ps, 20ps)
- Work as a team leader and support for other team members
Senior Physical Design Engineer
Synapse Design Automation Inc
10.2016 - 02.2018
- Successfully taped out 5 projects (Crax MP, Phoenix E2, Puppy, MT3367, Boar)
- Handled design from gate netlist to GDSII and fixed complex design issues
Physical Design Engineer
Synapse Design Automation Inc
10.2015 - 09.2016
- Successfully taped out a project 28nm (Baseband) for ST Microelectronics
- Developed flow for synthesis and performed PnR implementation
Physical Design Engineer
Uniquify Inc
10.2014 - 10.2015
- Successfully taped out first project 28nm (DragonX)
- Developed flow for synthesis and performed PnR implementation
Education
Electronics and Telecommunications -
Ho Chi Minh City University of technology - Vietnam National University
Skills
Project leadership
Agile methodology
Design development
Technical analysis
Mentorship and coaching
Team leadership
Technological advancement
Issue investigation
Debugging techniques
Problem-solving abilities
Multitasking
Programming languages: TCL, Perl, Python, C-shell
Selfassessment
For backend design, I can skillfully operate including:
- Physical Design implementation from RTL to GDSII.
- Expertise with multiple tools including Synopsys, Cadence, Mentor, Ansys - Redhawk, Dorado.
- Experienced in many special IPs like DDR4 slice, DDR4 PHY top, Serdes channel.
- Handling the complex design with over 20 power domains, 400+ macro and 3M of instances.
- Manage the PPA (power, performance, area) optimization to meet stringent design target.
- Detailed experience with bump plan, IO sequence, RDL route, ESD insertion, power plan, PLL placement.
- Expertise on fixing timing, DRV, PV, IREM, LEQ, VCLP, PERC…etc
- Proficiency in scripting languages such as Tcl, Perl, Python and Shell to automate design tasks and optimize workflows.
- Experienced in multiple process technologies, including TSMC 3nm, 5nm, 7nm, 12nm, 16nm, 28nm, 40mn and 45nm.
Basicinfo
Thanh Phat Phan, Male, 10/18/91, 10+ years, California, CA, thanhphatbk09@gmail.com, +1 (669) 234-2386, English, Vietnamese
Timeline
Senior Physical Design Technical Lead
Quest Global Inc
01.2022 - Current
Staff Physical Design Engineer
Synapse Design Automation Inc
02.2019 - 12.2021
Physical Design Lead
Synapse Design Automation Inc
03.2018 - 01.2019
Senior Physical Design Engineer
Synapse Design Automation Inc
10.2016 - 02.2018
Physical Design Engineer
Synapse Design Automation Inc
10.2015 - 09.2016
Physical Design Engineer
Uniquify Inc
10.2014 - 10.2015
Electronics and Telecommunications -
Ho Chi Minh City University of technology - Vietnam National University