Thanh Phat Phan

With over 10 years of experience spanning from RTL design to GDSII, I am proficient in operating EDA software from Cadence, Synopsys, and Mentor. Additionally, I have the ability to analyze and develop tools and scripts using Perl, TCL, Python and Shell to support design processes.

For backend design, I can skillfully operate including: 

- Physical Design implementation from RTL to GDSII. 

- Expertise with multiple tools including Synopsys, Cadence, Mentor, Ansys - Redhawk, Dorado. 

- Experienced in many special IPs like DDR4 slice, DDR4 PHY top, Serdes channel.

- Handling the complex design with over 20 power domains, 400+ macro and 3M of instances. 

- Manage the PPA (power, performance, area) optimization to meet stringent design target. 

- Detailed experience with bump plan, IO sequence, RDL route, ESD insertion, power plan, PLL placement. 

- Expertise on fixing timing, DRV, PV, IREM, LEQ, VCLP, PERC…etc 

- Proficiency in scripting languages such as Tcl, Perl, Python and Shell to automate design tasks and optimize workflows. 

- Experienced in multiple process technologies, including TSMC 3nm, 5nm, 7nm, 12nm, 16nm, 28nm, 40mn and 45nm.