Overview
Work History
Education
Skills
Timeline
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THOMAS PAULSON

Ham Lake,MN

Overview

54
54
years of professional experience

Work History

Emulation Engineer

Shakopee, MN
03.2014 - Current
  • Verification Engineer experienced in model and testbench development for ASICs working with verification technologies including Palladium, Protium, OVM and software simulators.
  • Qualifications Develop models for the Palladium Implement assertions for functional coverage Develop testbenches for the Palladium Develop OVM model components such as drivers, Verification planning for unit and system verification monitors and data items Evaluate tools to improve the verification process Implement methodologies for unit and system Technical leader for verification group verification Knowledge of the verification process for ASIC design Accomplishments Developed Makefiles and Scripts for building, running and debugging on the Palladium.
  • Also build with vendor IP delivered in both standard cell netlists and/or Palladium gate level netlists.
  • I worked closely with Cadence AE's and R&D to solve critical RTL build or run issues.
  • Developed testbench to interface DDR and Flash memories to the Palladium.
  • This included adding RTL for dq/dqs clock skew.
  • Developed testbench for interfacing Denali memories to the Palladium using IXCOM.
  • This was a firmware requirement to emulate with the same memory models on the Palladium as were simulated in VCS.
  • Developed models for Fibre Channel and Ethernet switches including speeds and protocols such as FC8G, FC16G, ETH10G, ETH20G and ETH40G.
  • The models were developed in verilog and system verilog with features for random packet size, random packet destinations and self-checking.
  • The models were used in both the Palladium and OVM test environments.
  • Developed testbench models for the Palladium.
  • This required the models to be synthesizable and have parameters to test ASIC features including steering modes, cache and tcam operations, buffer sizes and events injection.
  • Assertions were also implemented in the Palladium testbenches for better functional coverage.
  • Developed clock skew methodologies for testing smoothing fifos using the Palladium.
  • Clock testing requires longer run times that can be done more accurately in the Palladium.
  • Developed an OVM methodology for block/system testing to replace the current direct test system.
  • This included component development such as drivers, monitors and data items.
  • Assertions were added to this environment for better functional coverage.
  • Responsible for build and bring-up of SOC designs for the Palladium.
  • The SOC designs included IP from vendors, along with RTL developed internally.
  • Responsibilities also include maintaining the Palladium system, along with coordination and interface with Cadence.
  • In addition, I did a 3 month evaluation on the Protium and successfully emulated the most current design and firmware.
  • I was able to demonstrate a 10x performance improvement for the Protium over the Palladium.
  • The evaluation included using hdlice flow for the RTL, build for the Protium, and place/route for the Protium FPGA's.
  • The evaluation also included a Cadence provided DDR memory (xdram) interfaced to the DUT.
  • I was able to add probes for waveforms and set breakpoints for debugging.
  • As part of the evaluation, I debugged the Protium netlist on the Palladium.

Emulation Engineer

Shakopee, MN
08.2013 - 03.2014
  • Provide emulation support for internal and external projects for AMD.
  • This includes building emulation systems and initial bring up of these systems.
  • These systems are build and tested on he Palladium PXP and PIII hardware.
  • This work also includes debugging the design and test environment, debugging and writing SDL code tor the Palladium, and interfacing to internal and external customers.

Verification Engineer

QLogic Corporation
Shakopee, MN
12.1999 - 08.2013
  • Responsible for development and technical leadership for ASIC verification.
  • Developed models and testbenches for the ASIC verification for both NC-sim and the Palladium.
  • The Palladium was used on 7 ASIC projects, with all projects producing first-pass silicon.
  • The models were for a Fibre Channel/Ethernet switch and included modules for 8b/10b and 64b/66b encoding/decoding, scrambling, marker insertion and alignment.
  • In addition assertions were added to both the OVM and Palladium environments for better functional coverage.
  • Responsible for developing an OVM methodology for block/system level testing of a Fibre Channel/Ethernet switch.
  • Developed drivers, monitors, data items and virtual interfaces, along with sequence libraries and configuration objects.
  • This effort resulted in a better test environment for finding problem within the ASIC then the current direct test environment.
  • Critical design bugs were found and fixed using the models in both the OVM and Palladium environments.

Development Engineer

Summit Design
Fridley, MN
04.1997 - 11.1999
  • Developed co-verification models for system simulation.
  • This included developmental of BFMs to interface with the co-verification software.
  • This software produce was used to model hardware and software systems together.
  • The languages were C and VHDL.

Verification Engineer

Ancor
Eden Prairie, MN
06.1995 - 03.1997
  • Developed system simulation models and testbenches for ASIC verification.
  • This was the first attempt at system simulation for Ancor and required testbench and test suite development for Fibre channel ASICs.

Firmware Engineer

Fridley, MN
12.1994 - 05.1995
  • Developed firmware for the D2+ pacemaker.
  • The firmware continually took measurements to make sure the pacemaker leads were completely implanted.
  • The firmware was written in a proprietary language used within Medtronic.

Firmware Engineer

Development Resource Group
Fridley, MN
05.1993 - 11.1994
  • Developed firmware for natural gas compressor to be used for delivering natural gas to gas stations.
  • My responsibility for the project was the LED interface used to control and test the compressor.
  • I made numerous trips to customers for testing and debugging the compressor firmware.
  • Also wrote code to graph the startup cycles for the compressor.
  • This was a startup funded by a local venture capital group .

Software Development Engineer

Integrity Engineering
Arden Hills, MN
04.1992 - 04.1993
  • Developed software in C/C++ for a circuit board analysis tool to be used for interconnect analysis.
  • This included translators for netlists for various vendors.
  • Also interfaced with potential customers to relate product features.
  • Demonstrated the tool at DAC.

Development Engineer

Computer Timing Products
Ham Lake, MN
04.1991 - 03.1992
  • Startup company for development of a new and advance static timing analysis tool for ASIC development.
  • Algorithms and coding models were developed and tested.

Design Engineer

Control Data Corporation
Arden Hills, MN
09.1971 - 03.1991
  • Designed Arithmetic Units (ALUs) for large scale computers.
  • Developed individual components such as adders, multipliers and divide circuits.
  • Developed algorithms for double precision operations.
  • Technical lead for ALU group.
  • Worked with vendors to develop circuit models for functional simulation and timing analysis.

Education

Bachelor of Science - Electrical Engineering

Marquette University

Skills

Skills Experience Total Years Last Used VHDL, Verilog, System Verilog, TCL, Palladium 15 CVS

Timeline

Emulation Engineer

03.2014 - Current

Emulation Engineer

08.2013 - 03.2014

Verification Engineer

QLogic Corporation
12.1999 - 08.2013

Development Engineer

Summit Design
04.1997 - 11.1999

Verification Engineer

Ancor
06.1995 - 03.1997

Firmware Engineer

12.1994 - 05.1995

Firmware Engineer

Development Resource Group
05.1993 - 11.1994

Software Development Engineer

Integrity Engineering
04.1992 - 04.1993

Development Engineer

Computer Timing Products
04.1991 - 03.1992

Design Engineer

Control Data Corporation
09.1971 - 03.1991

Bachelor of Science - Electrical Engineering

Marquette University

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