UPPALAPATI BHARGAV RAJU
Bengaluru,India
Summary
Results-driven Sustenance QA Test Engineer at Mindteck/NetApp with expertise in BMC and BIOS validation. Proven track record in executing regression tests and triaging failures, enhancing firmware stability. Recognized for effective collaboration and problem-solving skills, utilizing Python and Jira to streamline processes and improve testing efficiency.
Overview
5
5
years of professional experience
Work History
Sustenance QA Test Engineer
Mindteck / NetApp
Bengaluru, India
03.2025 - Current
- Executed sustenance and regression validation across storage platforms to enhance firmware stability and address customer-impacting issues.
- Perform BMC/BIOS integration testing, including upgrade/downgrade validation and post-upgrade behavior verification.
- Triage failures using console logs, SEL/EMS events, DME logs, and internal tool outputs; deliver clear defect reports with repro steps and evidence.
- Utilized DART DB for validation tracking and analysis, streamlining execution and triage workflows.
- Developed and implemented basic Python scripts/utilities to enhance validation tasks and increase execution efficiency.
- Collaborate using GitHub and internal tools (including chatbot-based support) for tracking, coordination, and faster triage.
- Worked on storage devices (motherboard + SSD/HDD) and encountered PCIe as the underlying high-speed interface used to connect storage and other peripherals. While optimizing and validating SSD performance, you also worked with NVMe, which is the storage protocol designed to run over PCIe (NVMe SSDs appear as PCIe devices and are managed through the NVMe driver stack
Platform Test Engineer
Tata Consultancy Services (TCS) / NetApp
Bengaluru, India
10.2021 - 03.2025
- Executed manual and automated tests, analyzed logs, and reported issues through Jira, qTest, and Confluence.
- Executed 770 test cases per release cycle to validate functionality and ensure quality.
- Conducted platform validation including: BIOS firmware testing: upgrade/downgrade validation, port verification; FPGA/SFPGA firmware testing: upgrade/downgrade validation, recovery support; OS installation and ONTAP-based feature validation (shell commands, platform checks).
- Executed system reliability testing: power cycle, reboot, graceful/ungraceful reset, longevity/stress runs.
- Validated hardware compatibility and supported configurations: I/O cards, drives, cables, mixed platform configurations.
- Facilitated firmware chip recovery for FPGA and utilized ByteBlaster for lab/testbed activities.
- Reported 40 identified product issues to improve product reliability and performance.
- Honored with Spot Award on two occasions for excellence in work.
Education
Bachelor of Science (B.Sc.) - Maths, Electronics, Computer Science
Parvathaneni Brahmayya Siddhartha College
01-2021
Intermediate - Maths, Physics, Chemistry
Sri Chaitanya Junior College
01-2018
High School -
Aravinda High School
01-2016
Skills
- BIOS validation
- Firmware upgrade/downgrade
- Post-upgrade validation
- Port verification
- Recovery workflows
- SEL/EMS event validation
- Failure triage
- Manual testing
- Test planning
- Test automation
- Automation execution
- Regression testing
- Black-box testing
- Test reporting
- Defect management
- Hardware configuration validation
- Linux
- Console/log analysis
- ITP setup
- Jira
- QTest
- Confluence
- GitHub
- Defect tracking
- Python
- Shell
- PCIe/NVMe
- Lab tracking tools
Accomplishments
- Executed approximately 770 test cases per release/cycle.
- Identified and reported 40 product issues.
- Recognized with Spot Award (2 times).
Project Highlights
- Firmware Validation (BMC/BIOS) — Upgrade/Downgrade & Post-Upgrade Health
Validated firmware upgrade/downgrade flows, verified post-update health and stability, and compared behavior across releases/nightly builds. Collected and correlated evidence using SEL/EMS events, console logs, DME logs, and internal tool logs to identify and report deviations. - Stress / Reset / Power-Cycle Qualification Executed stress suites including reboot/reset/power-cycle scenarios and long-duration runs. Performed failure triage, reruns, and applied correct recovery procedures to meet validation timelines.
- Lab/Testbed Support & Recovery
Supported testbed readiness and configuration (ITP setup, NVMe/Quarch setup) and assisted with recovery workflows, including FPGA-related recovery activities. - BMC Telemetry & Sensor Debug
Used BMC diagnostic tools for sensor and event validation:
ipmitool (sensors/SEL/event checks), envcmdtool (sensor inventory/state in BMC diag shell)
PCIe / NVMe Validation Tooling - Hands-on with PCIe/NVMe visibility and debugging tools:
PCIe: lspci, dmesg, aer-inject
NVMe: nvme-cli, iostat, smartctl
Timeline
Sustenance QA Test Engineer
Mindteck / NetApp
03.2025 - Current
Platform Test Engineer
Tata Consultancy Services (TCS) / NetApp
10.2021 - 03.2025
Bachelor of Science (B.Sc.) - Maths, Electronics, Computer Science
Parvathaneni Brahmayya Siddhartha College
Intermediate - Maths, Physics, Chemistry
Sri Chaitanya Junior College
High School -
Aravinda High School