Vidya Sagar Reddy Gopala

Lead Software Engineering team to architect and build a design system with fully automated generation and validation of 10+ design collaterals with 4X TAT improvement. Achieved substantial business results by excelling in management, negotiation, and integrating cutting-edge AI advancements into the hardware IP development process, while leveraging collaborative skills in a complex, cross-functional, distributed environment.

Designed and led the development of a new IP design environment integrated with data analytics, job monitoring, and health check capabilities to ensure high-quality IP design. Architected a unified IP design and validation dashboard to support end-to-end execution, significantly reducing downtime between processes.

Drove adaption of data analytics, web applications, CI/CD pipelines and visualizations for improved IP design quality and productivity. Architected and drove development of ML/DL solutions in hardware ecosystem to identify anomalies in design collaterals and improved quality by 3X.

Developed vendor-agnostic flows and utilities to support IP design generation using tools from multiple vendors, accommodating diverse customer needs. Boosted design engineers' productivity by 2X by providing support through this interface. Enhanced efficiency in qualifying design data by equipping engineers with tools for data analysis and visualization.