Yusuf Khan
Austin
Summary
Skilled in managing and conducting complex research projects across diverse scientific disciplines. Possess strong analytical abilities, adept at data collection, analysis, and interpretation to drive project objectives. Demonstrated capacity for critical thinking and problem-solving to advance scientific understanding and application. Contributed to significant improvements in research methodology and efficiency in previous roles, enhancing overall project outcomes.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Electrical Engineering Research Assistant
UTD
Richardson
08.2025 - 12.2028
- Collected and analyzed experimental data using MATLAB/Python to derive insights and support research objectives
- Contributed to design and testing of electrical circuits and systems, ensuring functionality and reliability
- Supported simulation and modeling of engineering systems, facilitating accurate predictions and validations
- Collaborated with faculty and graduate researchers on technical tasks
- Documented findings and contributed to technical reports
Education
B.S. - Electrical Engineering
University of Texas at Dallas
12-2028
Skills
- Signal Processing
- Circuit Design
- Embedded Systems
- Analog Circuitry
- FPGA
- Verilog
- Vivado
- ModelSim
- Icarus Verilog
- EDAPlayground
- C
- Python
- MATLAB
- Breadboarding
Certification
- Developing Applications in Python on AWS, AWS
- Responsive Web Design, freeCodeCamp
Projects
- Arduino-Based LED Roulette Wheel, Engineered embedded system simulating roulette with realistic deceleration, Designed timing algorithm for smooth LED sequencing, Integrated hardware (LEDs, resistors, push-button) with control logic, Applied randomization for unbiased outcomes; validated via TinkerCAD and hardware, Debugged circuit and logic issues, improving reliability
- 4-Bit Ripple Carry Adder (Verilog), github.com/yusufzkhan/4Bit-Adder, Designed combinational logic for binary addition with carry propagation, Simulated and verified outputs using ModelSim; analyzed propagation delay, Developed modular Verilog for scalability
- 4-to-1 Multiplexer (Verilog), github.com/yusufzkhan/4To1-Multiplexer, Implemented input selection using control signals, Verified functionality using ModelSim across all test cases, Optimized logic structure for clarity and efficiency
Activities
IEEE Member
Timeline
Electrical Engineering Research Assistant
UTD
08.2025 - 12.2028
B.S. - Electrical Engineering
University of Texas at Dallas