Abhishek Ramachandran

• Design and Verification Certification, Maven Silicon, 08/01/21, 02/01/22
• Introduction to VLSI Design, IIT Madras, edX, 05/01/22, 07/01/22
• SystemVerilog Assertions and Functional Coverage, Udemy, 08/01/22, 10/01/22
• VLSI Academy - Learn Verilog HDL & FPGA Design Flow, Udemy, 03/01/23, 04/01/23
• Introduction to VLSI Design, IIT Kharagpur, Coursera, 06/01/23, 09/01/23

Maven Silicon Training Centre, Advanced VLSI Design and Verification, Bangalore, India.

• Developed a strong foundation in advanced Verilog for RTL design, together with SystemVerilog and UVM for verification.
• Acquired skills in Assertion-Based Verification, using SystemVerilog Assertions (SVA) for robust code and functional coverage.
• Learned key concepts in Digital Electronics, Static Timing Analysis and ASIC design and verification methodologies.

RTL Design and Verification of a 1x3 Router

• Designed a router that routes data packets to three output channels using Verilog.
• Developed components: FIFO (3), FSM, Synchronizer, and register blocks, Developed testbench using System Verilog and UVM methodology from scratch.

Verification of an adder module via UVM

• Using UVM methodology, completely verify an adder module that takes in 2-bit serial inputs and 3-bit serial outputs ensuring 100 percent coverage reached on input vectors.