Principal Engineer
Qualcomm
- Contributed to diverse architecture and design roles as both an individual contributor and SOC lead.
- Led Virgo SOC development, delivering highest-end enterprise-class WiFi AP featuring industry-first 4x4 MU-MIMO SOC.
- Specified and developed debug capabilities for global WiFi/BT connectivity solutions within Coresight-compliant architecture.
- Researched RISC-V architecture, validating its potential as a replacement for ARM cores.
- Architected and implemented a configurable RISC-V CPU subsystem.
- Achieved widespread proliferation of RISC-V cores, marking the first adoption within QCOM in applications such as the SoC root-of-trust, DDR controller, sensor subsystem, always-on control processor, etc.
- Oversaw the development of QCOM's current global IoT SOC platform architecture and acted as the lead for the Debug and CPU workgroups.
