ASHMITHA MAHADEVAN
Hudson,USA
Summary
Verification engineer with 5 years experience in Pre-Silicon Hardware Verification Domain who is passionate in ensuring quality and accuracy. Currently,seeking Full-time opportunities of ASIC/IP/SoC Hardware Pre-Si Verification.
Overview
7
7
years of professional experience
Work History
Verification Engineer
Intel Corporation
01.2020 - Current
- Working in Fabric Interconnect IP as verification engineer
- Developed and executed verification plans for key features, including register validation, reliability, and serviceability (RAS) working closely with microarchitecture and design teams to align on functional and performance requirements.
- Developed configurable and reusable UVM sequences to drive comprehensive test scenarios for register and IP level validation, ensuring modularity and scalability across test environments.
- Designed and implemented a global functional check in scoreboard, enabling rigorous end-to-end validation and cross-feature consistency checks.
- Led performance validation and coverage enablement, ensuring that defined microarchitectural and system performance counters were accurately captured and triggered under varied stimulus.
- Proactively debugged RTL issues using waveform analysis and interactive Verdi session, achieving early ~99% pass rates in volume regressions.
- Wrote and maintained functional coverage models and collaborated with the team to close code coverage gaps, ensuring verification completeness.
- Analyzed CPS (Cycles per Simulation) for testlists and optimized them, leading to a 10–50% improvement in simulation throughput.
- Enabled power-aware simulation for required topologies and presented the design-val flow to the team.
- Mentored junior engineers on testbench architecture, register flows, and best practices, fostering a culture of technical rigor and continuous improvement.
Intern
Intel Corporation
Hudson, MA
02.2019 - 11.2019
- Ramped up on basic architecture of testbench environment and IP spec
- Analyzed coverage for source-destination pairs for the mesh with Perl and further categorized them as legal and illegal transactions.
- Drove coverage-based verification to achieve 100% hit rate by indentifying corner-cases that required directed tests and impossible scenarios that were waived .
ARM Embedded Technologies
06.2018 - 08.2018
- Studied the end-to-end implementation flow of A-Class CPU, focusing on power grid construction.
- Analyzed sleep signal distribution to optimize in-rush current and wake-up latency and designed custom switch chains to enhance power planning and eliminate redundancy.
- Explored multiple floorplan variations to improve routing resources and power-up efficiency and evaluated designs using static IR, dynamic IR, and in-rush current analysis metrics.
Education
Master of Science - Computer Engineering
Texas A&M University
College Station, Texas08.2019
Bachelor of Engineering - Electronics and Communication Engineering
College of Engineering, Guindy, Anna University
India04.2017
Skills
System Verilog, UVM, OVM, Verilog, SystemC, Perl, Tcl, Python, VCS, Verdi, DVT Eclipse, UPF
Projects
Verification of 4-core MESI based L1 Cache Coherent System (04/2019)
- Developed verification plan, SV based UVM testbench components such as monitor, scoreboard and other UVCs. to run testcases .Assertions and checkers specific to each feature caught 10 bugs and coverage analysis (functional and code) was done using IMC tool which achieved 100% closure.
Design and Verification of 8 bit Pipelined Adder using buffered H clock tree( 12/2017)
- Designed schematic and layout of 8 bit pipelined adder in Cadence Virtuoso. Performed DRC, LVS, cell characterization and optimized the circuit using logical effort & gate sizing. Reported maximum Operating Frequency, Input Capacitance and Power Dissipation.
Cache Replacement Policy(12/2017)
- Optimized Cache replacement on a C++ architecture using using Signature-based Hit predictor in C++., It was tested against 27 individual benchmark traces, giving a mean geometric speedup of 6.2% over LRU.
Timeline
Verification Engineer
Intel Corporation
01.2020 - Current
Intern
Intel Corporation
02.2019 - 11.2019
ARM Embedded Technologies
06.2018 - 08.2018
Master of Science - Computer Engineering
Texas A&M University
Bachelor of Engineering - Electronics and Communication Engineering
College of Engineering, Guindy, Anna University
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