Avilok Shrivastava

Results-driven Electrical Engineer specializing in ATE hardware and software, achieving a 20% reduction in test times and 27% increase in efficiency through innovative debugging solutions. Proven success in managing automation tools that enhance performance and reduce costs, eager to contribute to impactful engineering projects.

• Implemented mechanism to gather user data needed for faster silicon Debug, Intel, 2024/2025, Identified inefficiencies in the usage of tools used for automation. Developed new procedures to reduce the overhead by 10-12 weeks (about 3 months) per year.
• Debug tool development and enabling new testing capabilities, Intel, 2022, Enabled system tool level debug capability at HVM to identify silicon level bugs and issues earlier in the process resulting in 20% less test time and hardware cost reduction.
• Debug Hardware design simplification and cost reduction, Intel, 2021, Simplified the existing debug hardware and eliminated need for additional hardware thus resulting in cost reduction by 25% also reducing design complexity.
• Developed debug tool automation and collateral generation process, Intel, 2024/2025, Automated the generation of ATE test collaterals which are essential to identify project critical issues henceforth reducing the testing cost by 15% on all HVM products.
• Probe card PCB & package designs for HVM products, Intel, 2017-2019, Completed PCB/package designs involving defining design requirements, schematic capture, layout, and routing reviews along with PI & SI simulations for new generation HVM products.
• Design and development of New Hardware / Probing Technology for Silicon test, Intel, 2016, Collaborated with various internal groups to put in new first of a kind analog and digital circuits on the boards, new probe & package technology along with process development & production ramp.
• Power and signal design simulation, Intel, 2018, Performed power delivery and signal integrity simulations to ensure the hardware meets the required power & high-speed interface constraints for post silicon validation on all Intel products.

• Promoted based on exceptional contribution to the development of system-based tools, 2024
• Departmental and Organization award for enabling debug tool capability earlier in the manufacturing process, Intel, 2023
• Best of Demos in Intel annual technical conference among 3000 presenters, Intel, 2022
• Employee Award of Excellence, Intel, 2022-2025
• Recognition for making sure product delivery is achieved on-time with quality standards, 2019

• Intro to VLSI
• Advanced VLSI
• Microelectronic device fabrication
• Solid state devices
• Embedded systems
• Modern VLSI
• VHDL and programmable logic design
• Analog circuits and layout
• Computer architecture
• IC Digital circuit design
• Digital signal processing