Chungho Lee

Expertise in process development and integration, specializing in thin film and silicon device physics. Proficient in nanoscale charge storage device fabrication, including nanocrystal, SONOS, and flash memory technologies. Strong communication and multi-project management capabilities, with a track record of resolving complex issues and enhancing testing methodologies. Extensive hands-on experience in electrical, optical, and analytical characterization, including reliability testing and failure analysis.

• BOOKS
• C.Lee and E.C
• Kan, Handbook of Semiconductor Nanostructures and Nanodevices edited by A
• A
• Balandin and K.L
• Wang, volume 5, chapter 1, American Scientific Publishers, Los Angeles, CA, USA, 2006
• PRESENTATIONS
• C
• Lee and E
• C
• Kan, “Double layer nanocrystal memories,” CNF annual meeting, 2004
• C
• Lee and E
• C
• Kan, “Charge storage in metal nanocrystals,” 1st Annual CNS Nanotech
• Symp., May 2004
• C
• Lee and E
• C
• Kan, “Technology for self-assembled nanocrystals in memory units,” CNF annual meeting, Sept
• 2003
• C
• Lee and C
• J
• Kim, "The new low voltage BiCMOS Circuit", JSAP (The Japan Society of Applied Physics) annual meeting, 1993
• C
• Lee and C
• J
• Kim, "The new full-swing BiCMOS for low voltage operation", IEEK (The Institute of Electronics Engineers of Korea) conference, vol
• 16, no
• 1, 1993.

• PATENTS
• US 20240015992A1, D. Cao, M. Gloeckler, S. Grover, J. Hack, C. Lee, D. Lu, A. Varadarajan, G. Xiong, Z. Zhao, “PHOTOVOLTAIC DEVICES AND METHODS OF MAKING”, 2024
• US 20220285569A1, S. Grover, C. Lee, X. Li, D. Lu, R. Malik, G. Xiong, “THIN FILM STACKS FOR GROUP V DOPING, PHOTOVOLTAIC DEVICES INCLUDING THE SAME, AND METHODS FOR FORMING PHOTOVOLTAIC DEVICES WITH THIN FILM STACKS”, 2022
• US 20210376177A1, L. Chen, S. Grover, J. Kephart, S. Kniajanski, C. Lee, X. Li, F. Liao, D. Lu, R. Mallick, W. Wang, G. Xiong, W. Zhang, “Buffer Layers for Photovoltaic Devices with Group V Doping”, 2020
• US 9640679B2, B. Buller, M. Gloeckler, R. Shao, Y. Yang, Z. Zhao, C. Lee, “Photovoltaic device with oxide layer”, 2017
• US 9508874B2, B. Buller, C. Lee, R. Shao, G. Xiong, Z. Zhao, “Photovoltaic device and method of manufacture”, 2016
• US 20140024190A1, F. Cheung, H. Kinoshita, C. Lee, Y. Sun, C. Chang, “dual storage node memory”, 2014
• US 20130186453A1, Z. Zhao, D. Hwang, D. Marinskiy, Z. Zhang, C. Lee, M. Khatri, B. Buller, “MITIGATING PHOTOVOLTAIC MODULE STRESS DAMAGE THROUGH CELL ISOLATION”, 2013
• US 20130098435A1, Z. Zhao, B. Buller, C. Lee, M. Gloeckler, D. Hwang, S. Mills, R. Shao, “Hybrid contact for and methods of formation of photovoltaic devices”, 2013
• US 008455268B2, C. Lee, H. Kinoshita, K. Chang, R. Sugino, C. Chang, H. Wu, ”Gate replacement with top oxide regrowth for the top oxide improvement,” 2013.
• US 008329598B2, C. Lee, K, Chang, H. Kinoshita, H. Wu, F. Cheung, “Sacrificial nitride and gate replacement,” 2012.
• US 20110146785A1, B. Buller, M. Gloeckler, C. Lee, S. McWilliams, R. Shao, Z. Zhao, “Photovoltaic device including doped layer”, 2011
• US 7666739, C. Lee, A. Melik-Martirosian, H. Kinoshita, K.T Chang, S. Rinji, W. Zheng, “Methods for fabricating a split charge storage node semiconductor memory,” 2010.
• US 7622373, W. Zheng and C. Lee, “Memory device having implanted oxide to block electron drift, and method of manufacturing the same,” 2009.
• US 7564091, C. Lee, A. Melik-Martirosian, H. Kinoshita, K.T. Chang, J. Amol, M. Meng, “Memory device and methods for its fabrication,” 2009
• US 7259984, E.C. Kan, Z. Liu, C. Lee, “Multibit metal nanocrystal memories and fabrication,” 2008
• US 20090152669, L. Xue, X. Aimin, C. Yang, A. Hui, C. Lee, “Si trench between bitline HDP for BVdss improvement,” 2009.
• US 20090108330, M. Shen, C. Lee, H. Kinoshita, H. Wu, “Split charge storage node outer spacer process,” 2009.
• US 20090101963, M. Shen, S. Fang, W. Lo, C. Marrian, C. Lee, N. Cheng, F. Cheung, H. Wu, H, “Split charge storage node inner spacer process,” 2009.
• US 20090039405, N. Cheng, K. Chang, H. Kinoshita, C. Yang, L. Xue, C. Lee, M. Shen, A. Hui, H. Wu, “ORO and ORPRO with bit line trench to suppress transport program disturb,” 2009.
• US 20080268650, C. Lee, H. Wu, W. Lo, H. Kinoshita, “Triple poly-Si replacement scheme for memory devices,” 2008.
• US 20080149999, WO2008079775, C. Lee, A. Melik-Martirosian, W. Zheng, T. Thurgate, C. Chang, H. Kinoshita, K.T. Chang, U. Kim, “Semiconductor memory comprising dual charge storage nodes and methods for its fabrication,” 2008
• US 20080142875, WO2007089949, C. Lee, W. Zheng, C. Chang, U. Kim, H. Kinoshita, “Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes,” 2008.
• US 20080094074, M. Kim, N. Y. Shen, C. Lee, E.C. Kan, “Transistor with floating gate and electret,” 2008.
• US 20080061359, C. Lee, H. Kinoshita, Z. Krivokapic, W. Zheng, M.S. Chang, R. Sugino, C. Chang, “Dual charge storage node with undercut gate oxide for deep sub-micron memory cell,” 2008.
• US 718662 E.C. Kan, Z. Liu, and C. Lee, “Multibit metal nanocrystal memories and fabrication,” 2007.
• US 5804700, C. S. Kwon and C. Lee, “Device and method for self-diagnosis in air-to-fuel ratio sensor”, 1998.
• KR0450780, C. Lee and C. S. Kwon, "The driving circuit for plate type lambda sensor", 2004.
• KR0331436, C. Lee and C. S. Kwon, "Oxygen sensor", 2002.
• KR0189846, C. Lee and C. S. Kwon, "The heater control circuit", 1999.
• KR0176212, C.S. Kwon and C. Lee, "On board diagnosis method and system for A/F sensor", 1998.
• KR0176211, C. Lee and C. S. Kwon, "The driving circuit for the wide range A/F sensor", 1998.

• E. Sartor, R. Muzzio, C. Jiang, C. Lee, “Selective isolation of surface grain boundaries by oxide dielectrics improves Cd(Se, Te) device performance, Appl. Mat. Interf., 2025.
• L. Kujovic, X. Liu, M. Togay, A. Abbas, A. Law, L. Jones, K. Curson, K. Barth, J.W. Bowers, J.M. Walls, O. Oklobia, D. A. Lamb, S. Irvine, W. Zhang, C. Lee, T. Nagle, D. Lu, G. Xiong, “Development of ZnO buffer layers for As-doped CdSeTe/CdTe solar cells with efficiency exceeding 20%”, Adv. Ma. Tech., 2025.
• N. Rosenblatt, J. Hack, C. Lee, Y. Zhang, “Impacts of band edge fluctuations on CdSeTe solar cell performance and models”, APL Mat., 2024.
• E. K. Roy, A. Mamun, C. Lee, G. Xiong, H. P. Yoon, “Microstructural passivation of patterned Al2O3 back contacts on CdS/CdTe solar cells”, Adv. Mat. Interf., 2024.
• M. F. Miller, E. Sartor, A. Nahar, C. Lee, M. Reese, A. R. Arehart, “Impacts of non-ideal back contact on capacitance measurements in CdTe solar cells”, IEEE PVSC, 2024.
• L. Infante-Ortega, X. Liu, L. Kujovic, M. Togay, L. O. Jones, A. Abbas, J. W. Bowers, J. M. Walls, W. Zhang, C. Lee, T. Nagle, D. Lu, G. Xiong, O. Oklobia, D. A. Lamb, S. J. C. Irvine, “Optimising the thickness of sputtered SnO2 buffer layers for high efficiency CdSeTe/CdTe devices”, IEEE PVSC, 2024
• L. Kujovic, X. Liu, M. Togay, A. Abbas, K. Curson, L. O. Jones, J. W. Bowers, J. M. Walls, O. Oklobia, D. A. Lamb, S. J. C. Irvine, W. Zhang, C. Lee, T. Nagle, D. Lu, G. Xiong, “Ce-alloyed ZnO buffer layers for thin film CdSeTe/CdTe solar cell”, IEEE PVSC 2024.
• E. Sartor, T. Zhang, C. P. Muzzillo, C. Lee, R. Muzzio, Y. Gogotsi, M. O. Reese, A. D. Taylor, “Hierarchical transparent back contacts for bifacial CdTe PV”, ACS En. Lett, 2024
• L. Kujovic, X. Liu, A. Abbas,L. Jones, A. Law, M. Togay, K. M. Curson, K. Barth, J. Bowers, J. Walls, O. Oklobia, D. Lamb, S. Irvine, W. Zhang, C. Lee, T. Nagle, D. Lu, G. Xiong, “Achieving 21.4% Efficient CdSeTe/CdTe Solar Cells Using Highly Resistive Intrinsic ZnO Buffer Layers”, Adv. Funct. Mater., 2312528, 2023
• D. Kuciauskas, C. Perkins, M. Nardone, C. Lee, R. Mallick, G. Xiong, “Band Bending at CdTe Solar Cell Contacts: Correlating Electro-Optical and X-Ray Photoelectron Spectroscopy Analyses of Thin Film Solar Cells”, Solar RRL, 2023
• C. P. Muzzillo, M. O. Reese, C. Lee, G. Xiong, “Cracked Film Lithography with CuGaO2 Buffers for Bifacial CdTe Photovoltaics“, Nano Micro Small, vol 19, issue 28, 2023
• R. Mallick, X. Li, C. Reich, X. Shan, W. Zhang, T. Nagle, L. Bok R. Farshchi, C. Lee, J. Hack, S. Grover, N. Wolf, E. Bicakci, N. Rosenblatt, D. Modi, W.K. Metzger, D. Lu, and G. Xiong, “Arsenic-Doped CdSeTe Solar Cells Achieve World Record 22.3% Efficiency”, IEEE JPV, vol 13 No 4, 2023
• Kuciauskas, M. Nardone, A. Bothwell, D. Albin, C. Reich, C. Lee, E. Colegrove, “Why Increased CdSeTe Charge Carrier Lifetimes and Radiative Efficiencies did not Result in Voltage Boost for CdTe Solar Cells”, Adv. En. Mater., vol 13, issue 35, 2023
• B. Sartor, M. Reese, C. Muzzillo, C. Lee, A. Taylor, “Hierarchal Ti3C2Tx MXene and Aluminum Micrigrid Back Contacts for Bifacial CdTe PV”, IEEE 50th PVSC, 2023
• E. Roy, K. Powell, C. Lee, G. Xiong, H. Yoon, “Design and Fabrication of PERC-Like CdTe Solar Cells Using Micropatterned Al2O3 Layer”, IEEE 50th PVSC, 2023
• W. Metzger, D. Miller, R. Mallick, X. Li, W. Zhang, I. Wang, A. Polizzotti, T. Ablekim, D. Cao, D. Hamilton, J. Bailey, C. Lee, S. Grover, D. Lu, G. Xiong, “As-Doped CdSeTe Solar Cells Achieving 22% Efficiency With -0.23%/C Temperature Coefficient”, IEEE JPV, 2022
• J. Hack, C. Lee, S. Grover, G. Xiong, “Hole Transport Material for Passivated Back Contacts on CdSeTe Solar Cells”, IEEE 48th PVSC, 2021
• D. Kuciauskas, J. Moseley, C. Lee,” Identification of Recombination Losses in CdSe/CdTe Solar Cells from Spectroscopic and Microscopic Time-Resolved Photoluminescence”, Solar RRL, vol 5, issue 4, 2021
• D. Kuciauskas, S. Li, J. Moseley, D. Albin, C. Lee, A. Onno, Z. Holman, “Voltage Loss Comparison in CdSe/CdTe Solar Cells and Polycrystalline CdSeTe”, IEEE JPV, 12 (1), 2021
• J. Moseley, D. Krasikov, C. Lee, D. Kuciauskas, “Diverse simulations of time-resolved photoluminescence in thin-film solar cells: A SnO2/CdSeTe1-x case study”, JAP, vol 130, issue 16, 2021
• P. Su, C. Lee, G.-C. Wang, T. Lu, I. Bhat, “CdTe/ZnTe/GaAs heterostructures for single-crystal CdTe solar cells”, JEM, 2014
• D. Kuciauskas, D. Albin, J. Moseley, S. Li, P. Acajev, C. Reich, A. Munshi, A. Danielson, W. Sampath, C. Lee, “Microsecond Carrier Lifetimes in Polycrystalline CdSeTe Heterostructures and in CdSeTe Thin Film Solar Cells”, IEEE 47th PVSC, 2020
• B. Jacquot, C. Lee, Y.N. Shen, E. C. Kan, “Time-resolved charge transport sensing by chemoreceptive neuron MOS transistors (CvMOS) with microfluidic channels,” IEEE Sensors Journal, vol. 7, issue 10, pp. 1429-1434, Oct. 2007.
• T. H. Hou, C. Lee, and E. C. Kan, “Modeling of multi-layer nanocrystal memory,” DRC, pp. 221-222, June 2007.
• U. Ganguly, C. Lee, T.H. Hou, and E.C. Kan, “Enhanced electrostatics for low-voltage operations in nanocrystal based nanotube/nanowire memories,” IEEE Trans. Nanotechnology, vol. 6, issue 1, pp. 22-28, Jan 2007.
• T.H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, “Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering,”, IEEE Trans. Electron Devices, vol. 53, issue 12, pp. 3095-3102, Dec. 2006.
• T.H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, “Design optimization of metal nanocrystal memory—Part II: Gate-stack engineering,” IEEE Trans. Electron Devices, vol. 53, issue 12, pp. 3103-3109, Dec. 2006.
• U. Ganguly, V. Narayanan, C. Lee, T.H. Hou, and E.C. Kan, “Three-dimensional analytical modeling of nanocrystal memory electrostatics,” Journal of Applied Physics, vol. 99, pp. 114516-1 – 114516-6, June 2006.
• T.H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E.C. Kan, “3-D electrostatic modeling and impact of high-k control oxide in metal nanocrystal memory,” DRC, pp. 271-272, June 2006.
• C. Lee, T. Hou, and E. C. Kan, “Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating gate,” IEEE Trans. Electron Devices, vol. 52, issue 12, pp. 26972702, Dec. 2005.
• C. Lee, U. Ganguly, V. Narayanan, T. Hou, and E. C. Kan, “Asymmetric electric field enhancement in nanocrystal memories,” IEEE Electron Dev. Lett., vol 26, issue 12, pp.879881, Dec. 2005.
• C. Lee, T. Hou, and E. C. Kan, “Metal nanocrystal/nitride heterogeneous stack floating gate memory,” DRC, 2005.
• C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, “Self-Assembly of Metal Nanocrystals on Ultra-Thin Oxide for Nonvolatile Memory Applications,” J. Electronic Materials, vol. 34, no. 1, Jan. 2005.
• M. Kim, N.Y. Shen, C. Lee, and E.C. Kan, “Fast and sensitive electret polymer characterization by extended floating gate MOSFET,” IEEE Trans. Dielectrics and Electrical Insulation, vol. 12, issue 5, pp. 1082-1087, Oct. 2005.
• B.C. Jacquot, C. Lee, Y.N. Shen, and E.C. Kan, “Time-resolved ion and molecule transport sensing with microfluidic integration by chemoreceptive neutron MOS transistors (CvMOS),” IEEE Sensors, pp. 4, Oct. 2005.
• M. Kim, C. Lee and E. C. Kan, “A new technique for contact mechanics and friction in microstructures: controllable electrostatic repulsive forces from capacitive coupling to electret”, World Tribology Congress III, 2005.
• C. Lee, U. Ganguly, and E. C. Kan, “Characterization of number fluctuations in gate-last metal nanocrystal nonvolatile memory array beyond 90nm CMOS technology,” in Mat. Res. Soc. Symp. Proc., 2004, pp. D5.4.1-D5.4.6.
• U. Ganguly, C. Lee, and E. C. Kan, “Experimental observation of non-volatile charge injection and molecular redox in fullerenes C60 and C70 in an EEPROM type device,” in Mat. Res. Soc. Symp. Proc., 2004, pp. D7.5.1-D7.5.6.
• A. Gorur-Seetharam, C. Lee, and E. C. Kan, “The Effect of Gate Geometry on the Charging Characteristics of Metal Nanocrystal Memories,” in Mat. Res. Soc. Symp. Proc., 2003, pp. N3.28.1-N3.28.6.
• U. Ganguly, C. Lee, and E. C. Kan, “Integration of Fullerenes and Carbon Nanotubes With Aggressively Scaled CMOS Gate Stacks,” in Mat. Res. Soc. Symp. Proc., 2003, pp. N16.3.1N16.3.6.
• N. Y. Shen, Z. Liu, C. Lee, B. A. Minch, and E. C. Kan, “Charge-based chemical sensors: a neuromorphic approach with chemoreceptive neuron MOS (CMOS) transistors,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2171-2178, Oct. 2003.
• C. Lee, A. Gorur-Seetharam, and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: Advantage of single- and double-layer metal nanocrystals” in IEDM Tech. Dig., 2003, pp. 557-560.
• Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan “A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage,” IEEE Electron Dev. Lett., vol. 24, no. 5, pp. 345-347, May 2003.
• C. Lee, Z. Liu, and E. C. Kan, “Investigation on Process Dependence of Self-Assembled Metal Nanocrystals,” in Mat. Res. Soc. Symp. Proc., 2002, pp. F8.18.1-F8.18.6.
• Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystals memories-part I: device design and fabrication”, IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, Sept. 2002.
• Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part II: electrical characteristics”, IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1614-1622, Sept. 2002.
• Z. Liu, C. Lee, G. Pei, V. Narayanan and E. C. Kan, “Eluding metal contamination in CMOS front-end fabrication by nanocrystal formation process,” in Mat. Res. Soc. Symp. Proc., 2001, pp. A5.3.1-A5.3.6.

• Ph. D. program: (G.P.A.: 3.86/4.0) Silicon device fundamentals, microelectro mechanical system, introduction of solid state physics, integrated circuit design, VLSI digital system design, etc.
• M.S. program: (G.P.A.: 4.35/4.5) Solid state physics, integrated optics, VLSI layout algorithm, VLSI circuit, VLSI fault testing, etc.
• B.S. program: (G.P.A.: 3.86/4.5) Semiconductor device, electronic materials, electromagnetics, electric circuit, electronic circuit, integrated circuits, physics, chemistry, etc.

• CORNELL UNIVERSITY, Electrical and Computer Engineering, Ithaca, NY. 2004 Course: Nanofabrication (ECE336/536). Teaching Assistant.
• CORNELL UNIVERSITY, Electrical and Computer Engineering, Ithaca, NY. 2000 Course: Introduction to Microelectronics (ECE315/215). Teaching Assistant.