Summary
Overview
Work History
Education
Skills
Websites
Accomplishments
Certification
Languages
Timeline
Generic

Chunhua Hu

Plano,TX

Summary

Seasoned SoC architect with 20 years of experience leading the definition and development of complex, multi-core SoCs for a wide range of applications. Recent focus is building SoC for automotive Software-Defined Vehicles, including central ECUs, gateways and zonal MCU controllers. Proven track record of successfully executing 20+ unique SoCs from 45nm to 5nm technology node. Known for blending deep technical insight with strong communication and leadership to drive innovations in SoC architecture. Experienced with architectural design and collaboration with cross functional team to bring projects from vision to reality.

Overview

23
23
years of professional experience
1
1
Certification

Work History

Senior SoC Architect

Texas Instruments
03.2006 - Current
  • Led the definition and SoC specification for over 20 unique SoCs across wireless signal processing, industrial control and various automotive domains, including IVI, ADAS, and SDV platforms.
  • Architected multiple generations of automotive SoCs, from high-performance central ECUs and mid-tier gateways to low-power zonal MCU controllers
  • Outlined a scalable SoC framework, integrating chiplet-based routing, isolation mechanisms, and domain separation strategies
  • Designed modular SoC frameworks enabling reuse the same base compute SoC to build tiered performance profiles for central ECUs and adapting to diverse compute requirements across vehicle segments
  • Delivered guaranteed real-time data processing across safety-critical domains, leveraging hardware isolation, deterministic scheduling, and low-latency interconnects
  • Known for performance analysis and architecture optimization, driving measurable improvements in compute efficiency and system responsiveness
  • Collaboration cross-functionally with business development, hardware design, software, verification and packaging to align architecture with evolving standards such as ISO 26262, AUTOSAR, and Ethernet TSN
  • Established strong relationships with customers and gaining deep understanding of market and technology trend


Chip Architect

Erlang Technology
08.2002 - 03.2006
  • Served as lead SoC architect for high-performance interconnect chips used in core routers, enabling scalable data flow and robust network infrastructure
  • Defined system-level architecture and specifications for multi-protocol interconnects, optimizing latency, throughput, and reliability for enterprise-grade networking platforms
  • Contributed to early innovations in network-on-chip (NoC) and packet-based interconnect design, laying technical groundwork for future SoC architectures

Education

Ph.D. - High-Performance Core Router Design

Washington University in St. Louis
St. Louis, MO
05.2002

Master of Engineering - Wireless Communication

Beijing University of Posts And Telecommunications
Beijing, China
05.1998

Bachelor of Applied Science - Computer Networking and Telecommunications

Beijing University of Posts And Telecommunications
Beijing, China
05.1995

Skills

  • SoC Definition & Detailed SoC/IP Specification
  • Hardware and Software partition
  • Hardware Accelerator Engine Integration & Memory Bandwidth Management
  • Guaranteed Real-Time Data Processing
  • Overall Architecture Optimization
  • Functional Safety (ISO 26262, ASIL-D)
  • Security Architecture
  • Power Management
  • Automotive Protocols (CAN, Ethernet TSN, PCIe)
  • Software-Defined Vehicle Architecture
  • Chiplet Architecture & Modular Compute Scaling
  • Cross-Functional Leadership & Communication

Websites

Accomplishments

  • Promoted to Senior Technical Staff at Texas Instruments in 2020 for outstanding technical contribution and leadership
  • Recognized innovator with 25+ granted patents in various SoC architecture domains such as safety mechanisms, security frameworks, power management, and system-level solutions
  • Cited in 300+ academic publications on Google Scholar, with over half of citations in the past five years

Certification

Certified in Functional Safety by TÜV (2017)

Languages

English: Native/Bilingual
Chinese (Mandarin): Native/Bilingual

Timeline

Senior SoC Architect

Texas Instruments
03.2006 - Current

Chip Architect

Erlang Technology
08.2002 - 03.2006

Ph.D. - High-Performance Core Router Design

Washington University in St. Louis

Master of Engineering - Wireless Communication

Beijing University of Posts And Telecommunications

Bachelor of Applied Science - Computer Networking and Telecommunications

Beijing University of Posts And Telecommunications

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