Dhiraj Korada
AUSTIN,TX
Summary
Dedicated and results-driven ASIC Physical Design Engineer with over 19 years of comprehensive expertise in the semiconductor industry. Equipped with a proven track record of successfully delivering high-performance, low-power designs across a spectrum of complex projects. Proficient in all aspects of the Physical design flow, from RTL to GDS, with a keen focus on optimization and timing closure. Skilled in leading cross-functional teams, collaborating with stakeholders, and driving projects from concept to tapeout.
Seeking Product Engineering opportunities to apply expertise in physical design, alongside artificial intelligence and machine learning, driving innovation and addressing new challenges.
Overview
20
20
years of professional experience
Work History
Physical Design Engineer
Apple Inc
07.2017 - Current
- 7 Tapeouts of Various Apple Products - TSMC 7/5/3nm
- Collaborated with cross-functional teams to ensure smooth project execution and timely delivery of designs.
- Proactively driven multiple PPA improvement efforts
- Driving optimizations within team using tools like Tempus and Cerebrus
Principal Engineer / Mgr
Aricent ( Now Capgemini )
04.2011 - 07.2017
- 7 Tapeouts completed while at Broadcom, Toshiba, Intel and internal Turnkey projects - TSMC 65/45/28/20/16 nm and Intel 22/14nm
- Primarily responsible for executing internal Turnkey Physical design projects by coordinating teams across California , Texas and Bangalore
- Block/Partition and Ipcore level Physical implementation responsibilities at Intel , Broadcom and Toshiba.
- Multiple PPA activities driven along with implementation of high speed arm cores.
Physical Design Lead
ST Microelectronics
08.2009 - 03.2011
- 3 Tapeouts completed at ST Microelectronics - 55nm ST
- Responsibilities included Block level and Top level activities related to Physical Design implementation from Netlist to GDS including Physical verification and STA timing closure
- Various PPA optimizations done using Olympus tool for mcmm post route optimization.
Sr. Physical Design Engineer
Qualcomm inc
03.2004 - 07.2009
- 10 Tapeouts completed at Qualcomm - TSMC
- 90/65/45nm , IBM 65nm
- Top Level Floorplan and Physical design
- Worked on complex flat and hierarchical partitions where responsibilities included Netlist to GDS Physical implementation along with Physical verification and STA closure .
- Responsibilities included driving PPA related activities and driving MCMM optimization techniques in PnR flow
Education
Post Graduate Program - Artifical Intelligence And Machine Learning
University of Texas At Austin
Austin, TX2024
MS in Microelectronics -
Birla Institute of Technology And Science
Pilani , Rajasthan. India2008
BE in Computer Engineering -
Mumbai University
Mumbai , Maharashtra , India2002
Skills
- Cadence , Synopsys and Mentor Tools
- Floorplanning
- PnR
- CTS
- STA closure
- IR analysis
- PV closure
- Python
- Perl
- Tcl
Accomplishments
Recieved an award for Best paper in Magma Users summit - 2009
https://www.edn.com/magma-congratulates-winners-of-music-india-best-paper-awards/?utm_source=eetimes&utm_medium=relatedcontent
Awards
- Received Super Qualstar award in Qualcomm
- Received 6 Qualstar awards in Qualcomm for excellent execution
- Received Best performer award in Smartplay/Aricent in 2014
- Received Best technical leader award in Smartplay Aricent in 2015
- Received ACE award in Aricent for technical leadership - 2017
Timeline
Physical Design Engineer
Apple Inc
07.2017 - Current
Principal Engineer / Mgr
Aricent ( Now Capgemini )
04.2011 - 07.2017
Physical Design Lead
ST Microelectronics
08.2009 - 03.2011
Sr. Physical Design Engineer
Qualcomm inc
03.2004 - 07.2009
Post Graduate Program - Artifical Intelligence And Machine Learning
University of Texas At Austin
MS in Microelectronics -
Birla Institute of Technology And Science
BE in Computer Engineering -
Mumbai University