Gururaja Ghorpade
611, Grosvenor Ln, Aurora,USA
Summary
Results-driven Analog/Mixed-Signal Circuit Designer with 20 years of experience in high-performance product development. Expertise in low-power audio applications, gigabit Ethernet, automotive PHY products, and data converters. Proficient in layout execution, process node selection, and silicon validation, with a proven track record of leading teams from concept to volume production. Committed to delivering innovative solutions that ensure optimal performance and reliability.
Overview
23
23
years of professional experience
Work History
Sr Manager Analog Mixed signal design
KNOWLES
10.2023 - Current
- Achieved enhanced linearity and reduced noise in next-gen microphone ASIC design.
- Led team of 11 engineers in developing innovative MEMS sensors and packaging.
- Drove strategic roadmap planning for cross-functional teams to meet project goals.
- Managed vendor collaborations for ASIC and MEMS production efficiency.
- Secured design wins by engaging with customers to optimize hearing aid microphones.
Director
KNOWLES
09.2022 - 09.2023
- Led personnel at facility, enhancing team performance and operational efficiency.
- Developed product line teams to deliver diverse products on schedule.
- Facilitated cross-site collaboration for successful new product launches.
- Achieved high-performance ASIC designs for analog and digital microphone applications.
- Evaluated and selected foundries from 55nm to 300nm for optimal production outcomes.
- Designed low-power amplifiers integrated with MEMS interface for advanced applications.
Senior design Manager / Chip Lead + System Architect
MCE Group
03.2017 - 08.2022
- Established a self-sustainable design team to deliver products from India.
- Led cross-functional teams as Chip/Technical lead for low power ASIC projects.
- Created system-level calculations and derived requirement specifications for new products.
- Conceived innovative digital communication interface, eliminating the need for extra pads.
- Designed low power amplifiers interfacing with MEMS technology for enhanced performance.
- Engineered band gap reference and charge pump designs for efficient power management.
- Developed temperature sensor models and designed incremental ADC and fixed gain amplifiers.
- Spearheaded low power ASIC design for digital microphone products, enhancing performance.
- Designed low power Sigma Delta ADC and ASIC front-end amplifiers for MEMS integration.
- Executed high voltage charge pump designs and power management block solutions.
- Managed IO design and ESD debugging during silicon evaluation processes.
- Facilitated silicon debugging for performance failures and ensured ESD compliance.
- Coordinated foundry communications and selected appropriate process nodes for production.
Senior Staff Engineer
MCE Group
05.2016 - 02.2017
- Low power ASIC used for Digital Microphone product (M17015).
- Driving platform creation project to different foundry and process node from 180nm to 130nm.
- Establishing new lab for Silicon validation.
- Strengthening the team and Mentoring.
- Successful first silicon.
Staff Engineer / Gigabit Ethernet and Automotive connectivity Group
TEXAS INSTRUMENTS
09.2011 - 04.2016
- Delivered low power Gigabit Ethernet PHY transceiver operating at 10/100/1000 MHz.
- Designed clock scheme meeting specified jitter requirements for optimal performance.
- Implemented 250MHz and 1.25GHz PLLs for PHY and SGMII functionality.
- Engineered phase interpolator circuit for effective CDR loop management.
- Conducted Verilog-A modeling of sub-blocks, ensuring top-level analog simulations.
- Executed AMS simulations at chip level, ensuring robust performance validation.
Staff Engineer / Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
10.2009 - 09.2011
- Enhanced signal precision by designing 24-bit ultra-low noise ΣΔ ADC.
- Developed modulator architecture, achieving 21-bit noise-free resolution improvement.
- Designed CMOS switched-cap modulator and optimized input buffer changes.
- Engineered CMOS relaxation oscillator for reliable internal oscillator functionality.
- Implemented design supporting data rates up to 12KSPS efficiently.
- Collaborated with digital team to create flexible input multiplexer for new features.
Senior Engineer / Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
03.2006 - 10.2009
- Enhanced system reliability by co-designing background calibration for error correction.
- Implemented architecture for Analog Front-end design, optimizing sensor integration.
- Developed CMOS input multiplexer, improving flexible channel selection.
- Evaluated cap array modulation, reducing gain error significantly.
- Created clock scheme with relaxation oscillator for comprehensive system synchronization.
- Engineered CMOS Rail-to-Rail Input buffer, isolating sensors from load impact.
Senior Engineer / System LSI- Analog
SANYO LSI
11.2004 - 03.2006
- Achieved low power consumption through design of temperature sensor sub blocks.
- Generated analog output voltage from -30 to 100°C for precise temperature readings.
- Engineered constant-gm circuit and bandgap design for GSMC 0.15μ technology.
- Developed pipelined ADC architecture using 0.18μ/1.8V technology standards.
- Designed necessary amplifier circuitry to enhance ADC performance.
Design Engineer / FPD Controller – Analog
UNITED MICROELECTRONC SOLUTIONS LIMITED
02.2003 - 11.2004
- Developed 8-bit 205MSPS ADC using 0.18μ CMOS TSMC technology.
- Collaborated with team to specify ADC front-end components and circuits.
- Executed design implementation for efficient data digitization via ADC.
- Created scaled-down 10-bit 50MHz ADC version for targeted applications.
- Bangalore, India, contributed to innovative electronic design projects.
Education
MTECH - Microelectronics and VLSI Design
INDIAN INSTITUTE OF TECHNOLOGY
Kharagpur, IndiaSkills
- Analog design
- Analog and mixed signal
- Chip architect and lead
- Low-power design
- Vendor management
- System architecture
- Product management
- Customer engagement
- Team development
- Mentoring and leadership
PERSONAL INFORMATION
- Nationality: Indian
- Marital Status: Married
PATENT DETAILS
- Zero wire interface communication to replace I2C, Under discussion, 01/01/25
- Microphone self-diagnostics through ASIC, Under discussion, 02/01/25
- Novel Start-up circuit for bandgap reference to mitigate the parasitic effect., Under process, IDF-00732, 01/01/23
- Digital microphone with over voltage protection., US 11,897,762B2d, 02/01/24
- Microphone with slew rate controlled buffer, US 11,909,387B2, 02/01/24
- Low voltage feedforward current assist Ethernet line driver, US20160072735A1, 09/10/15
- Background sensor diagnostic for multi-channel ADC, US8884629B1, 11/11/14
- Low noise, high CMRR and PSRR input buffer, US8330537 B1, 12/11/12
- Background Calibration Method for Fixed Gain Amplifiers, US8330631B2, 12/11/12
- Capacitor rotation method for removing gain error in sigma-delta analog-to-digital converters, US7825838, 11/02/10
- Background calibration method for ADC, US7825837, 11/02/10
COURSEWORK
- Low power Low voltage designs for data converters by Dr. Andrea Baschirotto, Associated Professor, University of Salento
- CMOS Analog Circuit Design by Dr.Phillip E Allen, Professor, Georgia Institute of Technology
- ESD and Latch up protection by Dr.Phillip E Allen, Professor
- Workshop on CMOS (C9T5V) and BICMOS (ABCD5HV) by Dr.Phillip E Allen
TECHNICAL SUMMARY
- Assessing design specifications: Low power Audio, Sensor AFE and Ethernet Products
- CMOS Analog Design: Data converters, Charge pump, LDO, PLL, RX, TX, Bandgap and reference designs
- Layout Execution
- Matlab Modeling
- VerilogA System Level Modelling
- AMS simulation: Chip level mixed signal simulations and verification
- Industry standard CAD tools and Linux/Unix environments.
- Top Level floor-planning and guiding Layout designers
- IO ring analysis for ESD/CDM/Signal integrity
- Bench characterization
- Technology exposure from 350nm to 65nm
- Mentoring and Cross functional interaction and multisite co-ordination
HOBBIES AND INTERESTS
Initiative to support Bangalore Kidney foundation, Sports: Cricket, Table tennis, Handling Analog courses during free time
Languages
English
Full Professional
Timeline
Sr Manager Analog Mixed signal design
KNOWLES
10.2023 - Current
Director
KNOWLES
09.2022 - 09.2023
Senior design Manager / Chip Lead + System Architect
MCE Group
03.2017 - 08.2022
Senior Staff Engineer
MCE Group
05.2016 - 02.2017
Staff Engineer / Gigabit Ethernet and Automotive connectivity Group
TEXAS INSTRUMENTS
09.2011 - 04.2016
Staff Engineer / Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
10.2009 - 09.2011
Senior Engineer / Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
03.2006 - 10.2009
Senior Engineer / System LSI- Analog
SANYO LSI
11.2004 - 03.2006
Design Engineer / FPD Controller – Analog
UNITED MICROELECTRONC SOLUTIONS LIMITED
02.2003 - 11.2004
MTECH - Microelectronics and VLSI Design
INDIAN INSTITUTE OF TECHNOLOGY