Hanri Bouzari
Summary
System Validation and Product Test Development Engineer with over 20 years of experience in developing and integrating deep sub-micron SOC devices' test programs production, characterization, yield enhancement, and test time reduction. Skilled in qualifying products through collaboration with teams of Design, Product, DFT, Technology, QA, and yield enhancement engineering teams in high-volume global semiconductor manufacturing sites.
Goal-oriented [Job Title] driven to help students focus on learning by maintaining discipline and equipping teachers with successful classroom strategies.
Overview
28
28
years of professional experience
Work History
Senior Principal Semiconductor Engineer
Northrop Grumman Corp.
02.2018 - 05.2024
- Company Overview: Mission System, Advanced Technology Lab, Linthicum Heights, Maryland
- The Semiconductor Test Engineer is responsible for wafer and package-level semiconductor test activities
- This includes both new product test development and production test support of digital, analog, mixed-signal, or process control monitor devices
- Typical tasks include identifying and evaluating test hardware, designing and debugging probe cards and package test fixtures, verifying equipment operation and performance, troubleshooting issues, developing test code, documenting test plans and procedures, evaluating test data, training, and certification test technicians and operators, and performing continuous test improvements
- The Test Engineer will interface with test engineering peers, design engineers, product engineers, process engineers, and program managers to resolve issues, optimize test accuracy and capability, improve yields and tester throughput, and meet customer needs
- Mission System, Advanced Technology Lab, Linthicum Heights, Maryland
System Validation Engineer- Contract
Intel Corp.
04.2017 - 01.2018
- Company Overview: Santa Clara, California
- Implementing CPU sub System Characterization using a modified MVB evaluation board
- Conducting PCIe enumeration characterization using Analog Voltage rails of PCIe controller and PHY
- Working closely with the PCIe PHY team to debug and improve the Gen3 enumeration test
- Modified MVB-Module Validation Board with new sets of ECOs - Engineering Change Order
- Screening new device revs for 375 / 750MHz DDR, CPU, UART, DSP & PCIe using DS-5 ARM stream and Lautherbach JTAG
- Santa Clara, California
GPU Hardware – Post Silicon Validation Engineer – Contract
Qualcomm Inc.
03.2015 - 09.2016
- Company Overview: San Diego, California
- Worked closely with the Power Management team to debug and characterize a new current sensing of embedded PMIC
- Evaluated RMA units - GPU hangs at customer development boards
- Created binary dump and kernel log files in Android environment in MTP- Modem Test Platform debug board
- Executed and analyzed nightly or weekly regression runs to validate GPU blocks
- San Diego, California
System Validation Engineer- Contract
Intel Corp.
06.2013 - 02.2014
- Company Overview: Austin, Texas
- Expert in High-Speed I/O - MIPI DSI Protocol and debugging, including knowledge of relevant debug tools (MIPI protocol, scopes, logic analyzers, Chip Scope, D-CAT-DSI (Capture and Analysis Tool)
- Executed MIPI DSI Protocol Conformance and D-PHY Compliance testing across different Process Levels for Intel's upcoming Smartphone products
- Worked closely with other engineers to automate DSI tests on the bench environment and analyze the data
- Enabled MIPI DSI Protocol Conformance Test infrastructure by analyzing and help debugging various versions of D-CAT (DSI Capture and Analysis Tool)
- Austin, Texas
Product Development Engineer, ATaC (Advanced Test and Characterization) Functional Group - Contract
Advanced Micro Devices - AMD
01.2011 - 08.2012
- Company Overview: Austin, Texas
- Developed test programs to bring up functional CPU core patterns for post-silicon validation of next-generation Multi-core CPUs/GPUs microprocessor package device on Credence – Sapphire ATE
- Implemented Functional Regression techniques to validate post-silicon test patterns for worse-case limiters
- Performed and analyzed functional CPU and GPU patterns limiters and found worse case speed paths in silicon debug using ATE to generate scan dump (RTL codes) files and also used LICAT -AMD's laser tool in Failure Analysis to improve process performance margin considerably
- Developed Circuit Sensitivity- mini characterization ATE program flow in functional testing to eliminate engineering involvement
- Austin, Texas
Test Engineer, CMOS Imaging Sensor -Contract
Panavision Imaging
09.2010 - 01.2011
- Company Overview: Homer, New York
- Developed final and wafer level test programs for CMOS Imaging Sensor –DLIS 2K on Teradyne – IP750
- Published Test Program Overview and Preliminary test strategies to provide low-cost and effective solutions for high-volume manufacturing for the Product Engineering Department
- Developed and debugged functional test patterns for yield enhancement activities and collaborated closely with the design team for new pattern generation in the final test program
- Designed probe needle card and Probe Interface Board for TSK Prober
- Homer, New York
Test Engineer, Networking and Multimedia Group
Freescale Semiconductor
05.2004 - 12.2009
- Company Overview: Austin, Texas
- Integrated and sustained final test program to market POWERQUICC- PQ38K Network Processor device on ATE - Teradyne UltraFlex tester
- Integrated pre-qualification test program on ATE from a team of 5 engineers and released test programs to the Test and Product Engineer team in an offshore foundry site
- Developed and summarized characterization test suite Local Bus AC specs
- Implemented new sets of the scan, jtag, and fused patterns for the PQ38K Chartered test program
- Analyzed characterization data for FMAX and VDDMIN search with JMP
- Identified the root cause of a process shift in pre-qualification HTOL reliability stress test failure by implementing various characterization techniques and shmoo plots
- Austin, Texas
Test Product Engineer II
Maxim Integrated Products
11.2000 - 12.2002
- Company Overview: Dallas, Texas
- Developed, modified, and debugged mixed signal T1 Transceiver device silicon and final test programs on ATE – Teradyne Catalyst tester
- Characterized PLL of new products on bench test and correlated to ATE test program for production release
- Conducted yield enhancement, test time, and cost reductions, achieving the initial objectives of projects
- Converted test programs from one test platform to a different test platform
- Transferred and correlated test programs to offshore foundry sites
- Monitored production cumulative yield trends and improved yield flows
- Dallas, Texas
Senior Associate Product Engineer
IBM Microelectronics Corp
05.1996 - 11.2000
- Company Overview: Essex Junction, Vermont
- Established engineering and scientific analysis on problems such as fail signature analysis; coordinated physical failure analysis, and correlating fail modes and defects to process sector, in collaboration with DRAM Development Alliance-(IBM/IFX/Toshiba)
- Provided direction and assisted manufacturing in achieving program productivity by monitoring module yield learning, parametric test data analysis, and yield support with SAS
- Monitored 256Mbit SDRAM cumulative module yield resulting and improved fab baseline defects and yield performance
- Investigated relevant trends in DC parametric versus in-line measurement trends
- Conducted fail corner signature analysis and correlated to In-Line measurements for low-yield memory products
- Provided bit fail map analysis for the physical failure analysis team
- Essex Junction, Vermont
Associate Product Engineer
IBM Microelectronics Corp
05.1996 - 11.2000
- Company Overview: Essex Junction, Vermont
- Analyzed data for Process Window tests on new 16Mbit SDRAM designs with statistics software
- Tested, debugged, and modified memory products utilizing the Teradyne J997 Memory Tester
- Provided the necessary data analysis for the quality and reliability team's 16Mbit SDRAM and stacked memory functional testing
- Compared to other vendor SDRAM specifications, ensuring IBM memory products exceeded current market specifications
- Essex Junction, Vermont
Education
Lean Six Sigma Green Belt Certification -
Purdue University
West Lafayette, Indiana07.2011
Master of Science - Electrical Engineering Technology
Arizona State University
Tempe, Arizona08.1995
Skills
- Credence Sapphire-ATE & TCU
- Teradyne IGXL Ultra Flex
- IPJ750
- Advantest 93K-ATE
- Agilent /Tektronix DSA-13GHz
- CMOS Process Technologies
- Statistical Analysis
- DOE
- ANOVA
- JMP
- DataPower
- Galaxy
- MiniTab
- Memory Process and IC fabrication
- SPC
- GR&R
- C/C
- VB
- Perl
- Python
- Lean Six Sigma Green Belt
- Oscilloscope
- Spectrum Analyzer
- Multitasking
- Team collaboration
- Classroom management
- Verbal and written communication
- Relationship building and networking
- Instructional leadership
- Training and mentoring
- Team building
- Student discipline
- Lesson planning
- Safety and security procedures
- Operational planning
- Student achievement
- Documentation
- Community engagement
- Group and individual instruction
- Employee performance evaluations
- Goal planning
- Educational staff supervision
- Curriculum development
- Prioritization
- Program implementation
- Team bonding
- Performance improvement
- Process improvements
- Group facilitation and presentations
- Data-driven instruction
- Performance evaluations
- Codes of conduct
- Education excellence
- Communications expert
- Interpersonal strengths
- Opportunities identification
- Schedule oversight
- Regulatory compliance
- Standardized testing
- Technology integrations
- Curriculum standards
- Student performance data
- Annual reviews
- Curriculum development and oversight
- Standardized testing and scoring
- Teaching and learning assessments
- Academic instruction
- Performance standards and analysis
- Teamwork and collaboration
- Problem-solving
- Time management
Languages
English
Full Professional
Persian
Full Professional
Timeline
Senior Principal Semiconductor Engineer
Northrop Grumman Corp.
02.2018 - 05.2024
System Validation Engineer- Contract
Intel Corp.
04.2017 - 01.2018
GPU Hardware – Post Silicon Validation Engineer – Contract
Qualcomm Inc.
03.2015 - 09.2016
System Validation Engineer- Contract
Intel Corp.
06.2013 - 02.2014
Product Development Engineer, ATaC (Advanced Test and Characterization) Functional Group - Contract
Advanced Micro Devices - AMD
01.2011 - 08.2012
Test Engineer, CMOS Imaging Sensor -Contract
Panavision Imaging
09.2010 - 01.2011
Test Engineer, Networking and Multimedia Group
Freescale Semiconductor
05.2004 - 12.2009
Test Product Engineer II
Maxim Integrated Products
11.2000 - 12.2002
Senior Associate Product Engineer
IBM Microelectronics Corp
05.1996 - 11.2000
Associate Product Engineer
IBM Microelectronics Corp
05.1996 - 11.2000
Master of Science - Electrical Engineering Technology
Arizona State University
Lean Six Sigma Green Belt Certification -
Purdue University
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