NILESH G. PATIL

Mechanical Engineer with 12+ years of experience in semiconductor equipment engineering, Technical Product Support (TPS), R&D integration, system qualification, reliability improvement, and new product introduction across advanced semiconductor manufacturing environments. Experienced in supporting 200 mm and 300 mm wafer processing equipment including PVD, CVD, ALD, Etch, cleaning, surface preparation, electroplating, electropolishing, and wet processing systems. Strong background in equipment qualification, installation, maintenance, vendor engagement, facility integration, and performance optimization. Experienced in wet bench systems, chemical delivery and distribution infrastructure, fume hoods, exhaust systems, drain networks, waste chemical management systems, vacuum systems, thermal systems, pumps, and utility interfaces supporting semiconductor operations. Ability to collaborate with Process, Facilities, Manufacturing, Safety, Service, and Global Engineering teams to resolve complex technical issues, improve equipment reliability, increase uptime, and ensure compliance with EHS requirements. Skilled in troubleshooting, root cause analysis, SOP development, maintenance documentation, Management of Change (MOC), risk assessment, engineering change control, and semiconductor equipment safety protocols.

• Xi'an, China, 2019, Resolved critical tool performance issues for a piezoelectric material development program on PVD platforms., Worked closely with global engineering teams to restore system performance and project timelines.
• United States, 2024, Supported VELA ALD platform for precursor delivery and consumption optimization., Assisted in creation of tool manuals, maintenance procedures, equipment documentation, and operating guidelines.
• United States, 2025, Supported WLS program installation activities., Assisted E-Beam tool decommissioning, Supported laser tool installation phase II.
• United States, 2026, Supported Quantum qubits project involving integration of PVD chambers with high-temperature heater 650 deg C subsystems., Performed validation activities and engineering assessments for advanced development programs.

• Designed and validated custom bench-top semiconductor tools for R&D applications involving ALD, CVD, Etch, and process development activities.
• Ensured alignment with Process Engineering and Business Unit requirements throughout design and validation phases.
• Successfully enabled Very High Temperature (VHT) operation up to 750C within an Endura PVD platform.
• Introduced advanced lamp control solutions to improve thin-film deposition quality and reduce defectivity.
• Supported integration of mechanical, vacuum, thermal, fluid handling, and utility subsystems for new product development projects.

• Optimized performance across PVD, CVD, ALD, Etch, cleaning, and characterization platforms.
• Resolved high-impact field and development issues affecting process repeatability, stability, and productivity.
• Led technical investigations involving vacuum systems, pumps, thermal subsystems, fluid handling systems, sensors, actuators, and process support equipment.
• Conducted detailed RCA activities and implemented corrective and preventive actions.
• Improved equipment uptime, maintainability, reliability, and operational readiness through engineering improvements.

• Thermal Metal Etch using Organic Solvent-Based Cleaning Process.
• Solid State Battery (SSB) Technology Development.
• LPC Pre-Metal Clean Technology Development.
• CMP Pad material development

US 20220025192A1, Deposition of Film Developed 

-Pulse DC power methodology for deposition of thin films used in piezoelectric device applications.,

 -Improved deposition techniques using multilayer ferrous conductive and insulating materials.