PONNIAH ILAVARASAN
Portland,OR
Summary
Senior Engineering Leader with 25+ years at Intel and NVIDIA driving system–silicon–software integration across client, mobile, Chrome, and IoT platforms. Proven record delivering on time quality to ensure platform product life cycle (PLC) delivered on time including significant power improvements as part of product launch through strong cross-functional execution and global team leadership.
Overview
28
28
years of professional experience
Work History
Director/Project Lead, Chrome Power/Performance/Thermal Engineering
Intel
01.2021 - 07.2025
- Led global U.S. and India teams to define and execute Chrome OS platform power and performance strategy, aligning silicon, software, and ecosystem priorities.
- Delivered 10–15% sustained platform power reduction through silicon tuning and advanced core scheduling optimization—improving efficiency without performance tradeoffs.
- Founded and institutionalized the Intel–Google technical governance forum, enforcing KPI rigor, risk transparency, and launch readiness before feature enablement.
- Strategically balanced Chrome/Linux and Windows ecosystem requirements, safeguarding long-term silicon scalability and competitiveness beyond the Windows-centric roadmap.
Principal Technical Program Manager
Intel
01.2019 - 01.2020
- Directed end-to-end execution across hardware, software, firmware, and validation to achieve on-time, PLC-quality launch of Intel’s first big-core Chromebook platform—synchronized with the Windows ecosystem release.
- Influenced silicon architecture, design, validation, and manufacturing organizations to ensure Chromebook received equal technical prioritization, elevating non-Windows ecosystem parity at the silicon level.
- Safeguarded Chromebook power and performance by ensuring firmware silicon tuning optimized for Windows did not regress Chrome OS behavior—driving balanced EPP (Energy Performance Preference) tuning and cross-OS optimization.
- Resolved complex cross-functional resource conflicts through executive-level influence and direct engagement with senior engineers—driving collaborative solutions and alignment rather than escalations or mandates.
Staff Technical Program Manager
Intel
01.2017 - 01.2019
- Led delivery of Intel’s first successful heterogeneous (big.LITTLE) client architecture in close partnership with silicon architecture—establishing a scalable performance-per-watt foundation for future platforms.
- Unified silicon, platform, P-code/uCode, and OS governance under a single execution framework—enabling seamless pre-silicon to post-silicon validation and accelerated issue resolution.
- Chaired the Client Patch Board, driving prioritization and deployment of critical uCode/P-code updates across multiple silicon steppings to protect quality, performance, and customer commitments.
- Orchestrated cross–business unit architecture alignment to shape next-generation Client and IoT SoCs, ensuring cohesive roadmap execution and long-term scalability.
Engineering Manager, New Device Group
Intel
01.2014 - 01.2016
- Directed 100+ cross-functional engineers to deliver multiple first-time IP integrations on schedule, de-risking silicon bring-up and accelerating time-to-market.
- Instituted structured Vertical Team governance and a unified validation framework, eliminating redundant efforts, increasing execution predictability, and improving cross-functional accountability.
- Enabled early customer engagement and platform readiness through pre-silicon virtual environments, advancing ecosystem alignment and reducing post-silicon surprises.
Senior Staff Manager, Mobile Communications
Intel
01.2011 - 01.2014
- Influenced SoC and form-factor decisions through power/performance/thermal/mechanical leadership.
- Collaborated with Foxconn to develop a new phone design to test out the new technologies and thermal/mechanical bounds to deliver balanced power/performance using Intel SOCs.
- Was part of delivering first Intel phone in India and was part of debugging/resolving thermally induced skin temp issues by delivering automated algorithms to reduce the frequency without impacting performance greatly.
- Built high-performing US/Taiwan team and developed cross-org tools for power and validation.
Senior Engineering Manager / Platform Architect
NVIDIA
01.2007 - 01.2011
- Defined Board POR strategy across multiple chipset platforms, optimizing cost, feature set, and validation coverage to enable scalable, high-volume productization.
- Architected end-to-end system thermal solutions for Tegra tablets and smartphones—directly linking silicon power targets to chassis design, industrial constraints, and user experience.
- Led competitive platform tear-downs and translated findings into customer-facing thermal and EMC design guidance, strengthening design wins and accelerating OEM readiness.
Early Career: Desktop & Consumer Platforms
Intel
01.1998 - 01.2007
- Built and scaled EMC and wireless engineering teams in Malaysia, establishing state-of-the-art RF laboratories and securing ~$1.8M in capital funding to expand regional technical capability.
- Delivered the first fully integrated 802.11a/g PC platform and resolved complex Bluetooth/WiFi coexistence challenges, enabling robust wireless performance and accelerating OEM adoption.
- Developed and deployed Design-for-EMC automation tools that improved design review efficiency 20x and reduced compliance test time by 60%, elevating OEM quality ratings from C to A and strengthening customer confidence.
Education
Ph.D., M.S., B.S. - Electrical Engineering
Michigan State University
Skills
- Cross-Organizational Program Leadership
- SoC/Platform Power, Performance & Thermal
- Architecture-to-Execution Alignment
- EMI/EMC & System Integration
- OEM/ODM Customer Engagement
- Relationship building
- Decision-making
- People management
- Strategic planning
- Project management
- Creativity and innovation
- Employee development
Executive Value
Proven execution leader driving seamless alignment across architecture, silicon, software, and customers to deliver first-time-right products with quantifiable gains in power, quality, and cost.
Timeline
Director/Project Lead, Chrome Power/Performance/Thermal Engineering
Intel
01.2021 - 07.2025
Principal Technical Program Manager
Intel
01.2019 - 01.2020
Staff Technical Program Manager
Intel
01.2017 - 01.2019
Engineering Manager, New Device Group
Intel
01.2014 - 01.2016
Senior Staff Manager, Mobile Communications
Intel
01.2011 - 01.2014
Senior Engineering Manager / Platform Architect
NVIDIA
01.2007 - 01.2011
Early Career: Desktop & Consumer Platforms
Intel
01.1998 - 01.2007
Ph.D., M.S., B.S. - Electrical Engineering
Michigan State University