Varun Munjal
San Jose,CA
Summary
Staff-level SoC and mixed-signal systems architect with 18+ years of experience defining and delivering complex silicon subsystems spanning camera, sensor, and display processing pipelines. Proven track record of driving architecture decisions across performance, power, area, and physical implementation through cross-functional collaboration with design, validation, firmware, and silicon bring-up teams. Experienced in converting ambiguous product requirements into objective engineering tradeoffs that guide architectural decisions, with a consistent track record of first-pass silicon success across multiple tape-outs.
Overview
18
18
years of professional experience
Work History
Display SoC Architecture
Apple
01.2020 - Current
- Defined architecture and led modeling and validation for multiple display processing IP blocks deployed across custom SoCs powering several iPhone, iPad, and Mac product generations.
- Defined quantization strategy and microarchitectural precision for image processing pipeline stages, balancing image quality, memory bandwidth, power, and silicon area.
- Reduced pipeline area for a complex image reconstruction IP by 25% through architectural tradeoffs in numerical precision and dynamic range without measurable image quality impact.
- Established objective evaluation frameworks for image quality tradeoffs, reducing subjectivity in architectural decisions around quantization, bandwidth, and compute precision.
- Defined perception-based acceptance criteria to validate image processing IP against feature and quality requirements.
- Drove cross-functional architecture decisions across RTL design, DV, firmware, and silicon bring-up teams.
- Represented display IP architecture in SoC integration reviews aligning subsystem requirements with system-level bandwidth and platform constraints.
- Authored Engineering Requirements Specifications for the display pipeline powering Apple’s Studio Display XDR.
- Partnered with design, validation, firmware, and silicon bring-up teams to ensure architectural assumptions held through implementation, contributing to successful first-pass silicon bring-up.
- Architecture & System Design
- Modeling, Infrastructure & Execution
- Architected and deployed a Python and SystemC-based modeling framework integrating bit-accurate C models, MATLAB references, configuration generation, HW/FW co-simulation, regression infrastructure, and CI workflows.
- Developed automation tooling for generating validation collateral, reducing validation time by 2–3 weeks and enabling reuse across the team’s workflow.
- Leveraged cross-functional experience to anticipate integration risks and guide architecture decisions aligning design, firmware, and validation teams.
- Mentored engineers and led architecture reviews for 5+ years.
Principal Engineer / Manager
RED Digital Cinema
01.2008 - 01.2020
- Defined system-level sensor architecture including noise, power, interface bandwidth, and image quality tradeoffs for global shutter sensor design.
- Owned full-chip composition including block integration, floorplanning strategy, and power/signal routing coordination.
- Led custom analog and mixed-signal circuit design, verification, and layout.
- Drove tape-out planning and cross-functional execution across design, verification, layout, and foundry teams.
- Built Xilinx Ultrascale-based FPGA prototyping platform enabling early architecture validation.
- Managed three engineers responsible for wafer probing, package test, and camera calibration supporting high-volume production.
Education
M.S. - Integrated Circuit Design
UCLA
B.Tech. - Electrical Engineering
IIT Delhi
Skills
- SoC Architecture & Subsystem Integration
- Performance / Power / Area Tradeoffs
- Hardware / Software Partitioning
- Quantization Optimization & Bit-Depth Trade Studies
- Python & SystemC-Based Architectural Modeling
- High-Speed Interface Architecture (DisplayPort, MIPI, Multi-Gigabit SerDes)
- Analog & Mixed-Signal Design
- Full-Chip Composition & Tape-Out Leadership
- Silicon Bring-Up & Post-Silicon Debug
- FPGA Prototyping
Timeline
Display SoC Architecture
Apple
01.2020 - Current
Principal Engineer / Manager
RED Digital Cinema
01.2008 - 01.2020
B.Tech. - Electrical Engineering
IIT Delhi
M.S. - Integrated Circuit Design
UCLA