Amruta Desai
Portland,OR
Summary
Accomplished technical leader with over 15 years of experience in physical design engineering and more than 10 years in leadership roles, steering teams through RTL to GDS2 implementation for NextGen Client and SoC products. Proven expertise in physical design and timing signoff, demonstrating a track record of effective planning, execution tracking, issue resolution, and communication. Renowned for empowering team members, consistently meeting tight schedules and PPA targets, and adeptly managing die size constraints. Proficient in all design phases, including synthesis, floor-planning, place and route, extraction, timing, and physical verification. Recognized for exceptional project communication skills, successful collaboration with globally dispersed teams, and skillful coordination with CAD, RTL/design, architecture, power & performance, packaging, and other internal and external stakeholders.
Overview
16
16
years of professional experience
Work History
SoC Physical Design Domain Lead
Intel Corp
04.2022 - Current
- Lead a team of skilled SoC Engineering Managers responsible for subsystems in Intel's NextGen Client and SoC projects.
- Proven expertise in planning, execution tracking, issue resolution, and communication, with a strong ability to meet tight schedules and PPA targets. Skilled in managing die size constraints and overseeing all design phases, including synthesis, floor-planning, place and route, extraction, timing, and physical verification.
- Collaborate closely with interdisciplinary teams, including CAD, Logic, Power and Performance, as well as other internal and external partners.
SoC Design Engineering Manager & Physical Design Lead
Intel Corp
07.2018 - 04.2022
- Manage, coach, and mentor a team of skilled SoC Engineers focused on Physical Design for Intel's NextGen Client and SoC projects
- Lead and deliver the Physical Design aspects of SoC dies, which include multiple subsystems and partitions
- Collaborate with cross functional teams like Logic, timing and full chip for SoC Physical Design planning.
Sr SoC Design Engineer/ Tech Lead
Intel Corp
04.2014 - 07.2018
- Held various technical leadership positions working on Physical Design aspects on critical SoC projects
- Mentored several SoC Design Engineers on Synthesis and Place/Route flows
- Led planning and execution work groups for cluster level designs on 10nm node
- Led physical design methodology pioneering of the Synthesis and Place/Route flows using industry standard tools on critical SoC projects
- Owned the physical implementation of complex partition from RTL2GDS2 for various projects (Intel 14nm, 10nm process nodes)
- Experience in handling blocks with multiple power domains, placement, routing and timing challenges.
SoC Design Engineer
Intel Corp
03.2010 - 04.2014
- Owned and delivered multiple high-speed Functional unit blocks from RTL2GDS2 on 4th/5th gen Intel processors (Intel 22nm, 14nm process nodes)
- Demonstrated Excellent skills in analyzing floorplan problems and delivering workable solutions.
Graduate Technical Intern
Intel Corp
02.2009 - 02.2010
- Design and develop custom design of functional unit blocks involved in clock distribution network
- Involved in physical design floor planning, auto place and route, PV and LV for clock functional blocks.
Education
MS in Electrical and Computer Engineering -
University of Cincinnati
Cincinnati, Ohio03.2010
Skills
People Management
Technical Leadership
Problem solving and analysis
Teamwork and Collaboration
Organizational Skills
Logical Synthesis
Floorplaning
Auto Place and Route
Clock Tree Synthesis
Static Timing Analysis
Physical Design Verification
ECO implementation
Timeline
SoC Physical Design Domain Lead
Intel Corp
04.2022 - Current
SoC Design Engineering Manager & Physical Design Lead
Intel Corp
07.2018 - 04.2022
Sr SoC Design Engineer/ Tech Lead
Intel Corp
04.2014 - 07.2018
SoC Design Engineer
Intel Corp
03.2010 - 04.2014
Graduate Technical Intern
Intel Corp
02.2009 - 02.2010
MS in Electrical and Computer Engineering -
University of Cincinnati