Sabarinathan Natarajan
Marlboro,MA
Summary
SoC Physical Design Engineer with 12+ years of experience driving design quality and closure. Proven track record of delivering successful RTL-to-GDSII closure across low-power designs from 40nm to 2nm. Currently managing and mentoring a team of engineers while driving cross-domain execution and ensuring timely delivery through strong technical and program leadership.
Overview
15
15
years of professional experience
Work History
SOC Physical Design Engineer, P&R
Apple
Cambridge, MA
02.2021 - Current
- Work on all aspects of physical design and implementation of Hardware chips.
- Interface with architecture, CAD, timing, and logic design teams to deliver best in class physical design.
- Ensure adherence of physical construction including integration, physical verification, formal verification, static timing, and power integrity.
- Work with the frontend team on chip architecture and drive physical aspects early in design.
- Collaborate with the physical design team to drive methodologies and “best known methods”, streamline physical design work, create guidelines and checklists, drive execution, and track progress.
- Work with place and route engineers, set goals and milestones, plan short and long-term work and handle dependencies between different domains such as top, Static Timing Analysis (STA), block place and route. Resolve design and flow issues related to physical design, identifying potential solutions and driving execution.
- Manage and mentor a team of physical design engineers, providing technical guidance and support on project deliverables.
- Conduct regular 1:1s to track progress, address challenges, and provide performance feedback.
- Define and support short- and long-term career development goals for team members.
- Guide engineers on complex analysis flows, methodologies, and project execution.
- Support critical milestones by identifying risks, resolving issues, and ensuring timely delivery.
- Set team priorities, goals, and milestones, track execution across domains (top level, STA, block P&R, PDV and EMIR ).
- Promote team well-being by addressing work-life balance and fostering a productive environment.
- Assist in resource planning, task allocation, and performance evaluations.
Lead Physical Design Engineer
Altran
Hudson, MA
09.2019 - 02.2021
- Working on Intel 10nm rtl2gds closure for multiple SOC partitions.
- Developed DC topo recipes for improving ICC2 timing correlation.
- Devised custom placement recipes for critical high-speed buses across
SOC partitions. - Executed CTMESH/MSCTS flow closure across project for over 30
partitions. - Strategized CTMESH/MSCTS clock construction for critical clocks.
- Developed length-based layer constraints strategy for timing/routing
optimization. - Strategized critical power intent changes to RTL for improving
implementation QOR. - Provided analytic feedback to logic/timing/clock teams for various
design closure issues. - Reviewed clock latency and timing issues for SOC partitions, provided
optimal recipes for closure.
Lead Physical Design Engineer
Altran
Bangalore, India
05.2018 - 08.2019
- Worked for Intel 10nm block level rtl2gds closure and full chip eco closure.
- Taken lead role to drive block level closure with team size of 5.
- Implemented source synchronous path fixes and clock tree exceptions
for full chip timing fixes. - Built hold buffer reduction recipe by addressing skew issues.
- Created custom PG grid solutions to fix IR hot spots based on
PTPX-RH analysis. - Implemented EM/Thermal fixes based PTPX-RH based power model.
- Created various layout errors analysis/fixing recipes to address internal/interface layout errors.
- Integrated custom built IP's by closely with IP teams for timing/layout closure.
- Integrated full chip by absorbing functional/timing eco's, IR drop fixes with bump re planning.
Lead Timing Engineer
Altran
Bangalore, India
03.2017 - 05.2018
- Worked for Intel 14nm/10nm IP lib modeling and timing closure.
- Taken lead role to drive custom IP lib delivery with team size of 3.
- Created clock/timing spec by closely working with circuit owners for
custom IP lib requirement. - Created timing exceptions, xtalk/noise modeling for ETM libs, AOCV
vs POCV derate analysis. - Correlation analysis between NLDM lib and flat STA run to improve
ETM lib efficiency. - Strategized parasitic annotation issues handling and debug for various
implementation issues. - Created custom spef annotation from layout data to model pre layout ETM libs.
Physical Design Engineer
Altran
Bangalore, India
02.2016 - 03.2017
- Worked for Intel 14nm full chip/block level implementation and timing closure.
- Taken responsible to drive block implementations with team size of 4.
- Strategized execution plans and pull back schedule to meet project
deliverables. - Developed efficient clock skewing recipes memory-register paths.
- Built custom clock tree at full chip level to achieve target skew/latency
for sub blocks. - Strategized floorplan recipe to place sub blocks and special cells to
control timing through multiple blocks at full chip. - Implemented NDR/Shielding recipes for clock/analog and critical data
signals. - Worked on RDL routing based on load of sub blocks and bump/pad
locations. - Worked on strategizing timing eco's/layout feedback from signoff team.
Physical Design Engineer
Altran
Bangalore, India
10.2013 - 02.2016
- Worked for Broadcom 22nm/40nm block level implementation and timing closure.
- Devised floorplan recipe for multiple memory stacks and analog IP's.
- Incorporated floor director latency solutions flow to fix peak power reduction.
- Strategized source synchronous IO path fixes and IO data skew fixes.
- Worked on pre layout STA which includes constraints cleanup for design and IP's.
- Worked on timing closure along with US team through POCV based Goldtime-Tweaker flow.
- Improved area/leakage/dynamic power reduction by influencing tweaker power reduction flow.
- Strategized EM/IR violation fixes based on feedback from power team
Physical Design Trainee
Nanochip Solutions
Bangalore, India
02.2013 - 10.2013
- Worked for block level physical implementation and timing eco.
- Created placement recipes based on hierarchical grouping.
- Worked on spare cell placement and distribution across voltage island.
- Strategized voltage island size and spacing to meet timing requirements.
- Implemented floorplan channel spacing requirement to mitigate DRC issues during timing eco's.
Project Engineer
Foxconn
Chennai, India
01.2011 - 02.2012
- Worked in an industrial robotic assembly line for mobile phone panel manufacturer.
- Handled various robot sensing/control malfunctions for multi axis Yamaha robots.
Education
Advanced Diploma in ASIC Design: VLSI -
RV VLSI Design Center
Bangalore, India2012
Bachelor of Engineering: Electronics Communication -
Adhiparasakthi Engineering College
Tamil Nadu, India2010
Skills
- RTL2GDS low power implementation
- CTMESH/MSCTS construction
- Xtalk/Noise/Power analysis
- POCV/LVF aware timing closure
- Layout verification
- TCL scripting/automation
- Implementation: DC/DCT/ICC/ICC2
- Signoff: PTSI/ICV/PTPX/RH
- FEV/LP: Conformal/Spyglass
- People Management, Mentoring and Resource Planning
- Technical Leadership (Physical Design)
- Risk Identification & Problem Solving
- Process & Methodology Improvement
- Team Development & Well-being
Timeline
SOC Physical Design Engineer, P&R
Apple
02.2021 - Current
Lead Physical Design Engineer
Altran
09.2019 - 02.2021
Lead Physical Design Engineer
Altran
05.2018 - 08.2019
Lead Timing Engineer
Altran
03.2017 - 05.2018
Physical Design Engineer
Altran
02.2016 - 03.2017
Physical Design Engineer
Altran
10.2013 - 02.2016
Physical Design Trainee
Nanochip Solutions
02.2013 - 10.2013
Project Engineer
Foxconn
01.2011 - 02.2012
Bachelor of Engineering: Electronics Communication -
Adhiparasakthi Engineering College
Advanced Diploma in ASIC Design: VLSI -
RV VLSI Design Center