Danny (Yuanli) Ding

Next-generation Altera FPGA Memory Subsystem IP

• Implemented a logical-to-physical address mapping algorithm in Tcl that optimizes overall read/write efficiencies across all user applications and minimizes logical address holes based on next-gen Altera FPGA Network-on-Chip (NoC) architecture.
• Enabling memory subsystem example design and regression testing.

Agilex 7 M-Series NoC user flow enablement for High Bandwidth Memory (HBM2E) IP

• Enabled HPS to read and write HBM through NoC.
• Enabled programmable access privilege through target network interface units to protect HBM memory space.
• Exposed user access to NoC hardware performance monitors.

Agilex 7 F/I-Series Lookup IPs bug fixes, optimizations and test support

• Improved BCAM hashing algorithm to resolve hash collisions. The insertion failure rate is reduced from ~2% to 0% over 1000 simulation tests with 4,000,000 insertions in total.
• Updated TCAM lookup table depth parameterization, which reduces M20K usage by 50% on average for all the user configurations.
• Enabled EM-MBL simulation, timing and hardware tests with dual in-line DDR4s.
• Implemented an AXI traffic generator in Verilog that drives configurable patterns of management and search operations to Lookup IPs.

FPGA Acceleration Library

• Owned Level 1 BLAS primitives.
• Optimized a Gaussian Elimination linear system solver through batch-interleaving and systolic array implementations respectively for large and small matrices in OpenCL. Achieved a throughput increase of 80 times on average compared to the original implementations on Arria 10.
• Owned 100+ Statistic primitives that perform various data analysis in C++ HLS. Achieved a throughput increase of ~1.5 times on average compared to the original implementations on Arria 10.

Implemented a DDR3 memory controller in Verilog on Xilinx Vertex-7 to store pixel data from the camera.