JAGAT SHAH

Sr Architecture Verification Engineer, Full Chip SoC Team, 09/2022 – 07/2025

Led the design and implementation of complex object-oriented test environments, enabling the successful validation of 8+ high-profile projects across processor and chipset product teams, contributing to 100% on-time delivery of validated products.
• Developed and executed comprehensive validation test plans for key products, ensuring 99% first-pass silicon success and reliable product launches.
• Collaborated cross-functionally with CPU, Chipsets, and Full-Chip SoC teams, driving enhanced verification strategies and improving debugging efficiency, leading to 30% faster issue resolution.
• Played a pivotal role in validating cutting-edge products, including Microprocessors and chipset products for Power Management Control Units (PMCU), which accounted for over $500M in revenue.
• Led the integration and validation of multiple IP components at the full-chip level, ensuring seamless functionality across CPU and chipset architectures, including Power Management Control Units (PMCU) and Register Power Domain Translator (RPDT), enhancing overall system reliability by 25%.
• Owned end-to-end validation of key power and boot features such as Reset Exit, First Boot, Cold/Warm Reset, and advanced low-power modes (S0ix, Sxix), optimizing system power efficiency and ensuring stable transitions across 30+ power states.
• Spearheaded integration and validation for Save and Restore IP (RPDT), improving system recovery times by 40% during critical low-power state transitions.
• Fostered strong cross-team collaboration, reducing integration times by 20% and accelerating issue resolution by proactively streamlining validation processes and feedback loops.
• Mentored junior engineers, enhancing team productivity by 15% through continuous coaching and adoption of industry’s best practices of industry.

Sr Architecture Verification Engineer, Chipsets & IP Technologies Team, 03/2016 - 08/2022

Led functional validation for multiple chipset projects, ensuring flawless performance across products like Touch Host Controllers, Far Memory Host Controllers, and Gaussian Neural Accelerators, contributes to 20+ successful product launches.
• Developed and optimized UVM-based verification environments, resulting in 30% reduction in test bench development time and improved test reusability.
• Streamlined bug reporting processes, reducing debugging time by 25%, accelerating validation cycles, and ensuring faster product time-to-market.
• Authored comprehensive test plans, reviewed architectural specifications, and provided critical design feedback, enabling faster and more accurate validation of key product features.
Award: Intel Department Recognition Award (Chipset and IP technologies group) September 2019
• In recognition of your delivery of Intel’s First Touch Host controller on LKF and TGP-LP with zero silicon bugs.

Architecture Verification Engineer, Graphics Team, 01/2015 - 02/2016

Served as Integration Engineer for the Graphics Controller Subsystem Validation Team, ensuring seamless IP integration and validation of new and existing features.
• Updated test environments and integrated new IP versions, boosting the validation coverage by 35% and optimizing workflows for faster test execution.
• Authored and reviewed technical documentation, ensuring clarity and compliance with industry standards for facilitating smooth knowledge transfer within the team.

Architecture Verification Engineer, Microprocessor Team, 07/2005 - 01/2015

Served as Verification Engineer for major projects, including Penryn, Ivy bridge, Skylake, and Cannon Lake, driving high-quality validation for next-generation processors and contributing to $300M+ revenue.
• Delivered robust test environments for feature validation, eliminating regression failures and successfully root-causing RTL bugs, achieving 99% validation success on initial designs.
• Led PCIe controller validation, focusing on both digital and mixed-signal logic, earning numerous awards for timely project delivery and superior product excellence.
• Established strong client relationships through exceptional communication, aligning validation priorities with customer needs and contributing to 100% client satisfaction.
• Optimized engineering workflows, introducing innovative solutions that cut process bottlenecks by 15% and improved overall team efficiency.
Award: Intel Department Recognition Award (Microprocessor team) January 2015
• Award for outstanding contribution to the successful delivery of Intel’s first 22nm Microprocessor and 3rd generation Core Processor.

• Planned, Designed and taught three different courses in Electrical and Computer Science department for Graduate and Undergraduate students.
• Spring 2013: EEE285-CPE186 Micro computer System Design I.
• Spring 2020- Current: EEE280/CSC280 Advanced Computer Architecture.
• Spring 2024: CSC242 Computer Aided Systems Design and verification.
• Developed Class Presentation material, weekly assignments, monthly quizzes and projects to provide practical experience on subject matter.
• Challenged students to prove proficiency in subject matter through research project developments and presentations.
• Participated in professional development opportunities to stay current on best practices in education, applying new knowledge to enhance teaching effectiveness.
• Assessed student performance through a variety of evaluation methods, providing constructive feedback for continuous improvement.
• Contributed to the development of departmental goals and objectives by offering new courses on Systemverilog, aligning instructional efforts with institutional priorities.

• Responsible for the Verification for Products based on TCP/IP Communications and iSCSI HBAs.
• Developed comprehensive test cases to validate design specifications, increasing overall product quality.
• Implemented coverage-driven verification techniques for improved test effectiveness and resource allocation.
• Utilized advanced debug tools to effectively isolate issues within the hardware-software interface quickly and accurately.

• Delivered two successful TCPIP offload engine and PCI-Express Bridge products to the market through reliable FPGA and Post Silicon testing of the products.
• Improved software quality by conducting comprehensive testing, including functional, performance, and regression tests.
• Provided technical support to development teams and debugged test systems.
• Collaborated with cross-functional teams to identify potential risks and develop effective mitigation strategies during the testing phase.