Summary
Overview
Work History
Education
Skills
Accomplishments
Work Availability
Affiliations
Work Preference
Languages
Interests
Software
Timeline
Generic

John Huie

Hardware Customer Enabling Engineer
Phoenix,US

Summary

Dynamic engineering professional with extensive experience at Intel Corporation, excelling in project management and cross-functional teamwork. Proven track record in hardware design and debugging, driving significant improvements in product quality and operational efficiency. Adept at fostering collaboration and implementing innovative solutions to complex challenges, enhancing overall team performance and customer satisfaction.

Overview

48
48
years of professional experience
3
3
Languages

Work History

HW Customer Enabling Eng, TPM, PAE Lab Mgr

Intel Corporation
04.2017 - 09.2024

HW Customer Enabling Engineer: Focuses on ensuring the successful integration of Intel hardware products into customer solutions. This involves collaborating with customers, providing technical support, and enabling them to design and develop products using Intel technologies. They work closely with various teams, including sales, engineering, and product development, to address technical challenges, deliver training, and drive product adoption. It acts as a bridge between Intel's cutting-edge technology and its customers, ensuring successful product integration, and driving adoption.

Technical Program Management (TPM): Responsible for driving the execution of complex technical projects, leading cross-functional teams, and ensuring alignment with company strategy. Developing and executing project plans, fostering innovation, and delivering solutions that meet customer needs. Involved in various stages of the project lifecycle, from initial planning and design to implementation and validation.

Platform Application Engineer (PAE) Lab Manager: Leads the operation and management of global engineering labs, ensuring lab readiness, managing budgets, and driving efficiency. Responsible for standardizing processes, developing staff, and collaborating with cross-functional teams to align lab activities with business objectives. Includes overseeing the global support model, providing technical support to engineers, and ensuring the labs meet high standards of quality and efficiency.

Tool Design Engineer

Intel Corporation
04.2010 - 04.2017
  • Pioneered groundbreaking solutions to complex problems with creative approaches in materials selection, fabrication techniques, or assembly methods applied in new or modified tool designs.
  • Led training sessions on proper use of newly designed tools, ensuring safe operation and optimal performance among team members.
  • Elevated production capabilities through the integration of cutting-edge technologies into new and existing tool designs.
  • Enhanced tool performance by designing and implementing innovative concepts in collaboration with the engineering team.
  • Define tool requirements for PCI voltage and timing margining tool.
  • Reduced manufacturing costs through strategic optimization of tool designs for improved efficiency and production rates.
  • Spearheaded tool design standardization efforts, resulting in more easily interchangeable components and reduced production downtime.
  • Developed comprehensive technical documentation for each tool design project, providing a valuable resource for future reference.
  • Identified opportunities for cost reduction by analyzing material usage patterns and recommending alternative options when feasible.
  • Successfully completed numerous high-stakes projects under tight deadlines by employing exceptional time-management skills and a keen attention to detail throughout the design process.
  • Collaborated with cross-functional teams to develop robust tools that met unique customer requirements and specifications.
  • Drafted assemblies, models, and other technical drawings.
  • Tested newly installed systems, closely monitoring functionality and adherence to operating specifications.
  • Troubleshot and diagnosed silicon debug issues, and quickly made plans to fix the issue in the next silicon revision. Updated processes and test plans.
  • Provided critical support during production ramp-up phases, addressing any unforeseen challenges related to tool design or function effectively.
  • Supported continuous improvement efforts by actively participating in Lean Manufacturing initiatives aimed at enhancing operational efficiency across various departments within the organization.
  • Increased product quality by conducting thorough analyses of tooling functionality and identifying areas for improvement.
  • Effectively developed models, assemblies, and drawings using Cadence/Mentor PCB Tools and Python for system validation.
  • Created a tool ecosystem for Atom microprocessors.
  • Defined and standardized silicon debug requirements for DFx (DFT, DFE, DFD) IP chassis.
  • Mentor junior engineers on Intel board specification designs and layouts.

Platform and Silicon Validation Engineer

Intel Corporation
02.2008 - 04.2010
  • Implemented continuous improvement initiatives for validation processes, leading to enhanced product quality and cost savings.
  • Conducted root cause analysis on deviations during validation activities, enabling timely resolution of technical issues.
  • Documented entire validation process, noting changes or alterations completed.
  • Mentored junior engineers in best practices for validation engineering methodologies improving team skillsets.
  • Streamlined the revalidation process by identifying opportunities for consolidation or elimination where appropriate.
  • Managed multiple validation projects simultaneously while adhering to strict deadlines and budget constraints.
  • Led risk assessment meetings, offering input on assessments such as system impact, component criticality, data integrity, and other factors.
  • Trained and assisted staff in validation techniques, methods and testing processes.
  • Assisted in creating a centralized repository for all validation documents streamlining access for future reference.
  • Collaborated with cross-functional teams to resolve complex issues, resulting in reduced downtime and increased production output.
  • Reduced operational risks associated with validated systems through periodic review assessments and targeted revalidations when necessary.
  • Generated validation plans for Viewmont projects, setting specific temporal and budgetary goals for development and delivery.
  • Developed comprehensive validation master plans to ensure alignment across all projects and stakeholders.
  • Utilized statistical tools such as Six Sigma methodologies contributing to data-driven decision making during validation processes.
  • Collaborated with cross-functional teams for identification and resolution of validation issues.
  • Developed validation master plans, process flow diagrams and standard operating procedures.
  • Monitored and reported on test results and performance data to identify areas of opportunity for improvement.
  • Demonstrated new product features and functionality to project stakeholders.
  • Drove corrective actions to accomplish project closure and recurrence control.
  • Design, fabricate test vehicles to interface with Mentor and Cadence emulators.

Vice President of Advanced Silicon Technology

Intellasys
10.2004 - 12.2007
  • Led cross-functional teams for the successful completion of major projects, resulting in increased efficiency and client satisfaction.
  • Collaborated with senior management to develop strategic initiatives and long term goals.
  • Identified opportunities to improve business process flows and productivity.
  • Established a culture of continuous improvement, fostering innovation and driving sustainable growth across the organization.
  • Leveraged technology to automate workflows and streamline processes, resulting in increased productivity and cost savings across the organization.
  • Established and directed a successful program focused on asynchronous microprocessor silicon design, achieving 1 GHz speed, 90 nm, and power consumption of less than 2 watts.
  • Define and develop a multi-order spice transistor characterization model for analog validation.

Chief Systems Architect

General Dynamics
04.2002 - 10.2004

Drive, define, and design the first direct conversion software-defined radio (SDR) for the DARPA JTRS (Joint Tactical Radio System) program. DARPA awarded the SDR program to General Dynamics and their partners (BAE Systems, Rockwell Collins, and Thales).

Signal Integrity Engineer

Intel Corporation
03.1999 - 04.2002
  • Mentored junior engineers, contributing to their professional growth and development in the field of Signal Integrity Engineering.
  • Developed innovative solutions for challenging signal integrity problems, resulting in improved product performance.
  • Supported customer success through providing expert guidance on best practices for maintaining optimal signal integrity in their designs.
  • Streamlined production efficiency by establishing robust guidelines for layout techniques and routing strategies.
  • Analyze, create Intel patent impedance etch design to correct RAMBUS impedance mismatch.
  • Coordinate the development of the first signal integrity training program for Intel: a 110-page PowerPoint presentation.
  • Created a spreadsheet methodology to measure ground bounce in a silicon package.
  • Develop IBIS models for various silicon package programs.
  • Enhanced product reliability with rigorous testing and validation processes, ensuring signal integrity compliance.
  • Ensured successful product launches by collaborating closely with manufacturing teams to address signal integrity concerns during production rampup.

Hardware Architect Engineer

Motorola
01.1996 - 03.1999
  • Attended team meetings to resolve technical and project issues and review project schedules.
  • Maintained strong communication with clients throughout the design process to ensure alignment between their vision and the final product.
  • Researched materials to determine appropriate selection for projects.
  • Applied creative problem-solving skills to address unique challenges in the architectural design process.
  • Lead a team of 10 engineers to define detailed design requirements for the compute stage (64 CPUs and 32 data search engines) of the Celestri satellite constellation, comprising 63 LEO satellites.
  • Communicated with vendors and contractors to incorporate input into project designs.
  • Reviewed technical drawings developed by CAD technicians and drafters.
  • Developed comprehensive project documentation, including site plans, elevations, sections, and details for clear communication of design intent.
  • Coordinated with cross-functional teams to improve structure sustainability and design.
  • Maintained quality control standards and procedures for accurate and precise measurements, illustrations and documentation.
  • Championed use of cutting-edge technology in design processes, improving accuracy and efficiency.
  • Analyzed and applied new technologies to improve functionality of designs.
  • Participated in formal internal design reviews of proposed products and components.
  • Reduced project completion time with efficient resource allocation and effective communication strategies.

Post Silicon Validation Engineer

VLSI Technology
01.1992 - 01.1996
  • Enhanced product reliability by executing comprehensive post-silicon validation and debugging processes.
  • Contributed to on-time product delivery by efficiently completing post-silicon validation tasks within project timelines.
  • Provided valuable feedback to design teams, enabling the incorporation of improvements in future iterations of semiconductor products.
  • Spearheaded efforts to adopt cutting-edge validation tools and techniques, resulting in increased efficiency and a competitive edge for the organization.
  • Assisted in root cause analysis for identified defects, leading to timely resolutions and enhanced product quality.
  • Mentored junior engineers, fostering a collaborative work environment and promoting knowledge sharing among team members.
  • Ensured compliance with industry standards while conducting thorough assessments of semiconductor devices'' functionality and performance characteristics.
  • Optimized test automation frameworks, expediting the validation process and increasing overall efficiency.
  • Effectively communicated findings from post-silicon tests to relevant stakeholders, facilitating informed decision-making regarding product release schedules.
  • Supported system-level integration efforts, contributing to seamless interaction between hardware and software components.
  • Reduced customer-reported issues by identifying and addressing potential failures through rigorous post-silicon testing procedures.
  • Maximized resource utilization by analyzing test results data to identify opportunities for optimization across various subsystems within the device architecture.
  • Improved post-silicon validation methodologies by staying abreast of industry trends and incorporating best practices into daily operations.
  • Participated in design reviews, providing valuable input for robustness improvements at an early stage in the development lifecycle.
  • Accelerated time-to-market by refining test execution strategies to minimize redundancy without compromising on quality control measures.
  • Maintained detailed documentation of test results and resolutions, ensuring traceability and transparency throughout the validation process.
  • Implemented effective data tracking systems to monitor progress during the validation phase, enabling quick identification of bottlenecks and mitigation strategies.
  • Developed detailed test plans and cases to ensure comprehensive coverage of product features during the validation process.
  • Drove continuous improvement initiatives, streamlining post-silicon validation processes for increased productivity.
  • Collaborated with cross-functional teams for efficient issue resolution, resulting in improved product performance.
  • Generated validation plans for CHIRP, chipset, pcmcia, and dragonfly projects, setting specific temporal and budgetary goals for development and delivery.

Operations Manager

Microtest
10.1988 - 04.1992
  • Conducted regular performance reviews, identifying areas for improvement and developing action plans to address them.
  • Supervised operations staff and kept employees compliant with company policies and procedures.
  • Led hiring, onboarding and training of new hires to fulfill business requirements.
  • Developed and implemented strategies to maximize customer satisfaction.
  • Implemented quality control systems to boost overall product consistency and reliability.
  • Analyzed and reported on key performance metrics to senior management.
  • Analyzed data trends to identify potential bottlenecks in operations workflow, implementing strategies to mitigate risks accordingly.
  • Managed inventory and supply chain operations to achieve timely and accurate delivery of goods and services.
  • Developed strong relationships with vendors, resulting in better pricing and improved service quality.
  • Oversaw facility maintenance, ensuring optimal functionality of equipment and infrastructure at all times.
  • Spearheaded process improvements, resulting in increased productivity and reduced operational costs.
  • Reduced turnaround time for project completion through effective resource allocation and team management.
  • Championed safety protocols to maintain a secure working environment, reducing workplace accidents significantly.
  • Reduced budgetary expenditures by effectively negotiating contracts for more advantageous terms.

Engineering Technician

Digital Equipment Corporation, Motorola GED, Intertel
04.1976 - 10.1988
  • Streamlined workflow within the team through effective communication and collaboration with engineers, technicians, and management.
  • Assisted in training new team members on company procedures, policies, and technical skills necessary for their roles as Engineering Technicians.
  • Consistently met high-quality standards for all completed work while adhering to established timelines, ensuring client satisfaction with final results.
  • Mitigated potential project risks by proactively identifying and addressing areas of concern before they developed into significant issues.
  • Completed engineering projects and tasks within established timelines and budgets.
  • Provided technical support for engineering projects to support accuracy and deadline management.
  • Collaborated closely with engineers in developing new products or improving existing ones, providing valuable input from a technician''s perspective.
  • Showcased strong attention to detail in the preparation, assembly, and installation of intricate components supporting engineering projects.
  • Enhanced the accuracy of technical documentation by reviewing and updating schematics, diagrams, and manuals regularly.
  • Conducted research and gathered data on engineering components and systems.
  • Implemented quality assurance procedures to minimize non-conformances.
  • Read and interpreted blueprints, technical drawings, schematics, and computer-generated reports.
  • Drafted technical reports and documentation for engineering projects.
  • Reviewed technical drawings developed by CAD technicians and drafters.
  • Assisted with design and implementation of new engineering processes and procedures to optimize productivity.
  • Assisted with installation, calibration and testing of engineering systems.
  • Performed work according to project schedules and high quality standards.
  • Reduced downtime during projects by rapidly identifying and resolving issues with machinery or systems.
  • Actively participated in cross-functional teams addressing complex problems requiring multidisciplinary perspectives contributing to successful outcomes.
  • Played an instrumental role in reducing project costs by effectively managing resources such as materials inventory management.
  • Optimized machine operation parameters, leading to noticeable improvement in product quality and consistency.
  • Enhanced operational safety, leading review and update of workplace safety protocols in line with industry best practices.
  • Supported successful product certifications, meticulously preparing documentation and coordinating with regulatory bodies.
  • Developed and implemented customized inventory tracking system, reducing material waste and optimizing supply chain efficiency.
  • Conducted comprehensive failure mode and effects analysis to mitigate risks associated with new product launches.
  • Fostered culture of continuous improvement, organizing professional development workshops for technical team.
  • Contributed to development of patent-pending technology, performing critical experiments and data analysis to validate concept.
  • Conferred with engineers and designers to investigate and solve failure issues.
  • Reviewed existing electrical engineering criteria to identify necessary revisions, deletions or amendments to outdated material.
  • Trained new system users and employees in classroom type sessions to promote useful system knowledge and operations expertise.
  • Revamped systems and upgraded wiring, PLCs and drives to handle changing needs.
  • Completed in-depth performance tests of parts and systems undergoing design optimization in simulated environments.
  • Updated hardware and software platforms by implementing automation and efficiency improvements.
  • Interpreted test information to resolve design-related problems.
  • Devised and implemented updates and resolutions for handling risks, maintaining compliance and improving designs.

Education

No Degree - Engineering Technician

DeVry University
Phoenix, AZ
05.2001 -

Skills

Laboratory management

Accomplishments

    Reduce initial power-on customer silicon/platform debug from 2 months to 2 hours.

    Concept to reduce board stackup through copper reduction and ground flooding.

    Standardization of silicon debug IP chassis

    Standardization of remote lab access and data analysis globally for silicon validation platforms

    Develop tool ecosystem for Atom processors with the look and feel of server tool interface

Work Availability

monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Affiliations

  • Linkedin

Work Preference

Work Type

Full Time

Work Location

On-SiteHybridRemote

Important To Me

Healthcare benefitsPaid sick leave401k matchStock Options / Equity / Profit SharingWork-life balanceFlexible work hoursPaid time offWork from home option

Languages

English
Full Professional
Chinese (Cantonese)
Native or Bilingual
Spanish
Limited Working

Interests

Photography, Community Services, Volunteer, Reading

Software

Python, Linux, Windows, x86 assembly, forth

Timeline

HW Customer Enabling Eng, TPM, PAE Lab Mgr

Intel Corporation
04.2017 - 09.2024

Tool Design Engineer

Intel Corporation
04.2010 - 04.2017

Platform and Silicon Validation Engineer

Intel Corporation
02.2008 - 04.2010

Vice President of Advanced Silicon Technology

Intellasys
10.2004 - 12.2007

Chief Systems Architect

General Dynamics
04.2002 - 10.2004

No Degree - Engineering Technician

DeVry University
05.2001 -

Signal Integrity Engineer

Intel Corporation
03.1999 - 04.2002

Hardware Architect Engineer

Motorola
01.1996 - 03.1999

Post Silicon Validation Engineer

VLSI Technology
01.1992 - 01.1996

Operations Manager

Microtest
10.1988 - 04.1992

Engineering Technician

Digital Equipment Corporation, Motorola GED, Intertel
04.1976 - 10.1988
John HuieHardware Customer Enabling Engineer
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