Summary
Overview
Work History
Education
Timeline
Generic

SATISHBABU BODAKUNTA

Austin,Texas

Summary

  • Proficient in ASIC implementation, specializing in physical synthesis, PPA optimization, technology entitlement, standard cell library evaluation, physical design, methodology exploration, ECO implementation and block-level STA timing closure at sub-nanometer nodes.
  • Experienced in high-frequency, low-power CPU implementation, with hands-on expertise in logic/physical synthesis, QOR benchmarking, power budgeting, and driving optimization techniques for frequency and power (leakage/dynamic) optimization, ensuring quality physical design implementation.
  • Experienced in technology entitlement and benchmarking PPA across multiple foundry process nodes, PDK releases, and standard cell library variants. Collaborated closely with DTCO, Library, PD, CAD, and methodology teams to derive scaling factors for power and performance projections, and flagged aspects influencing PPA goals for resolution.
  • Collaborated with micro-architects to define micro-architecture, perform design feasibility, and conduct power, performance, and area (PPA) trade-offs, guiding RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations.
  • Extensive experience with multiple tapeouts, leveraging the latest Synopsys and Cadence design tools such as Fusion Compiler, Primetime, PTPX, Genus, Innovus, Formality, and Conformal. Proficient in scripting and programming languages including Perl, TCI, bash, Verilog, VHDL, and System Verilog.

Overview

12
12
years of professional experience

Work History

CPU Physical Design Engineer

Intel Corp.
12.2021 - Current
  • Physical design and implementation of custom CPU designs through synthesis, floor planning, bus/ pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
  • Collaborated with the logic design team to understand partition architecture, analyze architectural critical paths, and provide early RTL feedback, optimizing floor planning and physical implementation to meet schedule and design goals.
  • Devised and implemented custom optimized solutions to address timing, congestion, routing, and noise issues, generating optimized Gate Level Netlists with a strong focus on improving Timing, Area, and Power.

CPU Implementation Engineer

Qualcomm
09.2016 - 12.2021
  • Contributed to the development and delivery of a high-performance, low-power ARM-compliant CPU subsystem for premium-tier mobile SoCs at advanced nodes (sub-7nm). Responsibilities included PPAT analysis, physical synthesis, and low-power implementation targeting ambitious power, performance, and area goals.
  • Led the implementation of a high-frequency CPU core by generating quality netlists through synthesis, exploring various optimization techniques to push frequency within power targets. Collaborated closely with RTL design, physical design, and library teams to achieve optimal performance and meet PPAT targets.
  • Established low-power design methodologies to identify power-saving opportunities by deeply analyzing standard cell libraries and physical synthesis. Implemented various metrics and models to track performance per watt, active power, peak power, and idle/stall power for various CPU power benchmarks.
  • Conducted power analysis at different RTL stages for various netlist recipes using PTPX with RTL/0-delay VCD across different vectors to explore dynamic/leakage power tradeoffs. Analyzed the design to identify candidate registers and combinational cells based on data activity and clock toggles to improve dynamic power. Maintained a power dashboard across design milestones.
  • Performed design experiments and qualitative PPA analysis to improve results using techniques such as activity-based physical synthesis, standard cell and design profiling, multibit flops, low-power flops, data path optimization, and useful skews.
  • Assessed RISC-V compliant CPU cores for power, performance, and area in comparison to ARM cores.

Soc Integration Engineer

Intel
08.2013 - 09.2016
  • Worked on high-frequency multimedia block, including logic synthesis, floor planning, FEV, power intent verification (UPF), and timing convergence, to deliver high-quality netlist.
  • Generated unit-level signoff quality STA constraints for both functional and scan (test) modes at partition and chip levels, driving blocks through timing closure at both full chip and partition levels.
  • Assisted full chip timing (FCT) team as junior engineer by running full chip PV runs across all corners and modes, analyzing and triaging timing violations, and creating and enhancing several paranoia checks to guide timing closure metrics.

EDA Design Engineering Intern

ON Semiconductor
05.2012 - 12.2012
  • Benchmarked digital standard cell libraries by simulating standard cells of custom process design kits, establishing performance parameters and characterization results.
  • Performed regression tests to analyze and resolve errors in initializing CAD tools for custom design flows.

Education

Master of Science - Electrical and Computer Engineering

Arizona State University
Tempe, AZ
05.2013

Bachelor of Technology - Electrical Engineering

JNTU
Hyderabad , INDIA
05.2011

Timeline

CPU Physical Design Engineer

Intel Corp.
12.2021 - Current

CPU Implementation Engineer

Qualcomm
09.2016 - 12.2021

Soc Integration Engineer

Intel
08.2013 - 09.2016

EDA Design Engineering Intern

ON Semiconductor
05.2012 - 12.2012

Master of Science - Electrical and Computer Engineering

Arizona State University

Bachelor of Technology - Electrical Engineering

JNTU

Similar Profiles

CREATE PROFILE
SATISHBABU BODAKUNTA