SRIKAR MATAM
Milpitas,United States
Summary
Experienced micro-architect and RTL design engineer with a proven track record in handling high-frequency and low-power designs. Seeking challenging opportunities to enhance expertise and contribute to cutting-edge projects. Skilled in developing efficient and optimized designs, with a strong understanding of industry standards and best practices. Committed to delivering exceptional results, thriving in dynamic environments that foster innovation and collaboration.
Overview
9
9
years of professional experience
Work History
ASIC Design Engineer - Memory subsystem Micro-architect & RTL Design
Apple Inc.
03.2017 - Current
- Micro-architecture and RTL Design of various aspects of System Cache Controller
- Consistently improved Performance, Power and Area across multiple generations through architectural, design and floorplan improvements
- Led work group to re-architect and re-design critical parts of the IP achieving significant PPA improvements
- Led Power and Performance activity representing the IP as a whole with cross-functional teams in achieving Power and Performance targets
- Implemented various timing fixes in successful timing closure of high frequency and low power designs
- Debugged complex functional and performance issues - Pre and Post Silicon
- Collaborated effectively with Architecture, Performance modeling, Design Verification, Physical Design, SOC Integration teams in delivering on tight deadlines.
Internship - DDR Subsystem Characterization and Testing Engineer
Qualcomm Inc.
09.2016 - 02.2017
- Performed Automatic Test Equipment (ATE) testing and characterization of DDR memory controllers
- Analyzed collected test data to validate functionality for different process, voltage and temperature corners.
Teaching Assistant - EE560 Digital System Design, EE457 Computer Systems Organization
University of Southern California
08.2015 - 08.2016
- Selected as Mentor (Teaching Assistant) for sought after graduate level courses based on academic performance
- Mentored students by holding office hours, attending to lab assignments and grading exams/assignments.
Education
Master of Science in Electrical Engineering (Honors) -
University of Southern California (USC)
Los Angeles, CABachelor of Engineering (Electronics and Communications) -
Vasavi College of Engineering, Osmania University
Skills
Micro-architecture
RTL Design
System Verilog
Verilog
Memory Subsystem
PPA improvement
Static Timing Analysis
Technicalskills
Verilog, System Verilog, C, Perl, Synopsys Design Compiler, Cadence Genus, Synopsys Prime Time, Spyglass, VC LP, Synopsys Formality, ModelSim, Verdi, Indago
Projects
32 - Bit Tomasulo Processor with Out of Order Execution, In Order Completion - Verilog, Designed a 32 - bit Out of Order Execution, In Order Completion Tomasulo Processor using VHDL, Re-Order Buffer (ROB) for In Order Completion, Copy Free Check pointing (CFC), Free Register List (FRL), 2 bit Branch Prediction Buffer (BPB), Return Address Stack (RAS), Store Address Buffer (SAB), Store Buffer (SB) Directed Research under Prof. Gandhi Puvvada - EE560 Tomasulo Project - Verilog, Reduced the branch penalty in the Tomasulo processor by replacing the existing Branch Prediction Buffer (BPB) in the Dispatch stage with Branch Target Buffer (BTB) in the Instruction Fetch stage Simple Chip Multiprocessor - Verilog, Synopsys Design Compiler, Prime Time, Cadence Encounter, Designed a 4 node ring router, variable width 64 bit pipelined processor together with network interface components, NCSU 45nm technology, Place & route, Logical equivalence check, 100 MHZ Full Custom Design and Implementation of a General Purpose Pipelined Processor - Cadence Virtuoso, Spectre, Designed the Schematic and Implemented the Layout of a 5 - Stage Pipelined Processor with 8 x 32 Register File, 32 - Bit ALU, 8 - Bit Multiplier, 1024 Bit SRAM. Performs basic operations like ADD, SUB, MUL, XOR, OR, LOAD, STORE etc., Optimized the design for minimum Area Power Delay product FIFO Design with Clock Domain Crossing - Verilog, Designed a dual clock FIFO to solve the problem of Clock Domain Crossing using both Flow-Through and Pipelined BRAMs
Timeline
ASIC Design Engineer - Memory subsystem Micro-architect & RTL Design
Apple Inc.
03.2017 - Current
Internship - DDR Subsystem Characterization and Testing Engineer
Qualcomm Inc.
09.2016 - 02.2017
Teaching Assistant - EE560 Digital System Design, EE457 Computer Systems Organization
University of Southern California
08.2015 - 08.2016
Master of Science in Electrical Engineering (Honors) -
University of Southern California (USC)
Bachelor of Engineering (Electronics and Communications) -
Vasavi College of Engineering, Osmania University
Similar Profiles
Zayna Katherine ZarzourZayna Katherine Zarzour
Specialist at Apple Inc.Specialist at Apple Inc.
Alexis HerreraAlexis Herrera
Security Partner at Apple Inc.Security Partner at Apple Inc.
Mohamed Al-KowsMohamed Al-Kows
Sales Supervisor at Apple Inc.Sales Supervisor at Apple Inc.
Timothy FerryTimothy Ferry
Cook Level 3 at Apple Inc.Cook Level 3 at Apple Inc.
GBADEBO A. ALLIGBADEBO A. ALLI
Medical Office/Nurse Assistant at Humu Health INCMedical Office/Nurse Assistant at Humu Health INC